From: Hongtao Liu <crazylht@gmail.com>
To: Haochen Jiang <haochen.jiang@intel.com>
Cc: gcc-patches@gcc.gnu.org, ubizjak@gmail.com, jakub@redhat.com,
hongtao.liu@intel.com
Subject: Re: [PATCH] i386: Add ISA check for newly introduced prefetch builtins.
Date: Fri, 11 Nov 2022 09:52:56 +0800 [thread overview]
Message-ID: <CAMZc-byJFVaABKQWaofo_j-jc+6MTOLY34eVGnPqLPaYf2-Qzg@mail.gmail.com> (raw)
In-Reply-To: <20221109071302.78435-1-haochen.jiang@intel.com>
On Wed, Nov 9, 2022 at 3:15 PM Haochen Jiang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi all,
>
> As Hongtao said, the fail on pentiumpro is caused by missing ISA check
> since we are using emit_insn () through new builtins and it won't check
> if the TARGET matches. Previously, the builtin in middle-end will check
> that.
>
> On pentiumpro, we won't have anything that supports any prefetch so that
> it dropped into the pattern and then failed.
>
> I have added the restrictions just like what middle-end builtin_prefetch
> does. Also I added missing checks for PREFETCHI. Ok for trunk?
Ok.
>
> BRs,
> Haochen
>
> gcc/ChangeLog:
>
> * config/i386/i386-builtin.def (BDESC): Add
> OPTION_MASK_ISA2_PREFETCHI for prefetchi builtin.
> * config/i386/i386-expand.cc (ix86_expand_builtin):
> Add ISA check before emit_insn.
> * config/i386/prfchiintrin.h: Add target for intrin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/prefetchi-5.c: New test.
> ---
> gcc/config/i386/i386-builtin.def | 2 +-
> gcc/config/i386/i386-expand.cc | 11 +++++++++--
> gcc/config/i386/prfchiintrin.h | 14 +++++++++++++-
> gcc/testsuite/gcc.target/i386/prefetchi-5.c | 4 ++++
> 4 files changed, 27 insertions(+), 4 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/prefetchi-5.c
>
> diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
> index ea3aff7f125..5e0461acc00 100644
> --- a/gcc/config/i386/i386-builtin.def
> +++ b/gcc/config/i386/i386-builtin.def
> @@ -498,7 +498,7 @@ BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide1
> BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide256kl_u8", IX86_BUILTIN_AESENCWIDE256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID)
>
> /* PREFETCHI */
> -BDESC (0, 0, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT)
> +BDESC (0, OPTION_MASK_ISA2_PREFETCHI, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT)
> BDESC (0, 0, CODE_FOR_nothing, "__builtin_ia32_prefetch", IX86_BUILTIN_PREFETCH, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT_INT_INT)
>
> BDESC_END (SPECIAL_ARGS, PURE_ARGS)
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index 9c92b07d5cd..0e45c195390 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -13131,7 +13131,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
>
> if (INTVAL (op3) == 1)
> {
> - if (TARGET_64BIT
> + if (TARGET_64BIT && TARGET_PREFETCHI
> && local_func_symbolic_operand (op0, GET_MODE (op0)))
> emit_insn (gen_prefetchi (op0, op2));
> else
> @@ -13150,7 +13150,14 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
> op0 = convert_memory_address (Pmode, op0);
> op0 = copy_addr_to_reg (op0);
> }
> - emit_insn (gen_prefetch (op0, op1, op2));
> +
> + if (TARGET_3DNOW || TARGET_PREFETCH_SSE
> + || TARGET_PRFCHW || TARGET_PREFETCHWT1)
> + emit_insn (gen_prefetch (op0, op1, op2));
> + else if (!MEM_P (op0) && side_effects_p (op0))
> + /* Don't do anything with direct references to volatile memory,
> + but generate code to handle other side effects. */
> + emit_insn (op0);
> }
>
> return 0;
> diff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h
> index 06deef488ba..996a4be1aba 100644
> --- a/gcc/config/i386/prfchiintrin.h
> +++ b/gcc/config/i386/prfchiintrin.h
> @@ -30,6 +30,13 @@
>
> #ifdef __x86_64__
>
> +
> +#ifndef __PREFETCHI__
> +#pragma GCC push_options
> +#pragma GCC target("prefetchi")
> +#define __DISABLE_PREFETCHI__
> +#endif /* __PREFETCHI__ */
> +
> extern __inline void
> __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _m_prefetchit0 (void* __P)
> @@ -44,6 +51,11 @@ _m_prefetchit1 (void* __P)
> __builtin_ia32_prefetchi (__P, 2);
> }
>
> -#endif
> +#ifdef __DISABLE_PREFETCHI__
> +#undef __DISABLE_PREFETCHI__
> +#pragma GCC pop_options
> +#endif /* __DISABLE_PREFETCHI__ */
> +
> +#endif /* __x86_64__ */
>
> #endif /* _PRFCHIINTRIN_H_INCLUDED */
> diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-5.c b/gcc/testsuite/gcc.target/i386/prefetchi-5.c
> new file mode 100644
> index 00000000000..8c26540f96a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/prefetchi-5.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile { target { ia32 } } } */
> +/* { dg-options "-O0 -march=pentiumpro" } */
> +
> +#include "prefetchi-4.c"
> --
> 2.18.1
>
--
BR,
Hongtao
prev parent reply other threads:[~2022-11-11 1:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 7:46 [PATCH] Support Intel prefetchit0/t1 Haochen Jiang
2022-11-07 1:28 ` Hongtao Liu
2022-11-08 10:06 ` Jakub Jelinek
2022-11-09 2:30 ` Hongtao Liu
2022-11-09 7:13 ` [PATCH] i386: Add ISA check for newly introduced prefetch builtins Haochen Jiang
2022-11-11 1:52 ` Hongtao Liu [this message]
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