[PATCH v4] xtensa: Eliminate unnecessary general-purpose reg-reg moves

[PATCH v4] xtensa: Eliminate unnecessary general-purpose reg-reg moves

[Takayuki 'January June' Suwa]

Register-register move instructions that can be easily seen as
unnecessary by the human eye may remain in the compiled result.
For example:

/* example */
double test(double a, double b) {
  return __builtin_copysign(a, b);
}

test:
	add.n	a3, a3, a3
	extui	a5, a5, 31, 1
	ssai	1
				;; be in the same BB
	src	a7, a5, a3	;; No '0' in the source constraints
				;; The destination replaced is
				;;   irrelevant to the sources if the
				;;   destination constraint has '&'
				;; No CALL insns in this span
				;; Both A3 and A7 are irrelevant to
				;;   insns in this span
	mov.n	a3, a7		;; An unnecessary reg-reg move
				;; A7 is not used after this
	ret.n

The last two instructions above, excluding the return instruction,
could be done like this:

	src	a3, a5, a3

This symptom often occurs when handling DI/DFmode values with SImode
instructions.  This patch solves the above problem using peephole2
pattern.

gcc/ChangeLog:

	* config/xtensa/xtensa.md: New peephole2 pattern that eliminates
	the occurrence of general-purpose register used only once and for
	transferring intermediate value.

gcc/testsuite/ChangeLog:

	* gcc.target/xtensa/elim_GP_regmove.c: New.
---
 gcc/config/xtensa/xtensa.md                   | 49 +++++++++++++++++++
 .../gcc.target/xtensa/elim_GP_regmove.c       | 23 +++++++++
 2 files changed, 72 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/xtensa/elim_GP_regmove.c

diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index dd3fc37353b..1a6154c8ded 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -3048,3 +3048,52 @@ FALLTHRU:;
   operands[1] = GEN_INT (imm0);
   operands[2] = GEN_INT (imm1);
 })
+
+(define_peephole2
+  [(set (match_operand 0 "register_operand")
+	(match_operand 1 "register_operand"))]
+  "GET_MODE_SIZE (GET_MODE (operands[0])) == 4
+   && GET_MODE_SIZE (GET_MODE (operands[1])) == 4
+   && GP_REG_P (REGNO (operands[0])) && GP_REG_P (REGNO (operands[1]))
+   && peep2_reg_dead_p (1, operands[1])"
+  [(const_int 0)]
+{
+  basic_block bb = BLOCK_FOR_INSN (curr_insn);
+  rtx_insn *head = BB_HEAD (bb), *insn;
+  rtx dest = operands[0], src = operands[1], pattern, t_dest;
+  int i;
+  for (insn = PREV_INSN (curr_insn);
+       insn && insn != head;
+       insn = PREV_INSN (insn))
+    if (CALL_P (insn))
+      break;
+    else if (INSN_P (insn))
+      {
+	if (GET_CODE (pattern = PATTERN (insn)) == SET
+	    && REG_P (t_dest = SET_DEST (pattern))
+	    && GET_MODE_SIZE (GET_MODE (t_dest)) == 4
+	    && REGNO (t_dest) == REGNO (src))
+	{
+	  extract_constrain_insn (insn);
+	  for (i = 1; i < recog_data.n_operands; ++i)
+	    if (strchr (recog_data.constraints[i], '0'))
+	      goto ABORT;
+	  if (strchr (recog_data.constraints[0], '&'))
+	    for (i = 1; i < recog_data.n_operands; ++i)
+	      if (reg_overlap_mentioned_p (dest, recog_data.operand[i]))
+		goto ABORT;
+	  SET_DEST (pattern) = gen_rtx_REG (GET_MODE (t_dest),
+					    REGNO (dest));
+	  df_insn_rescan (insn);
+	  goto FALLTHRU;
+	}
+	if (reg_overlap_mentioned_p (dest, pattern)
+	    || reg_overlap_mentioned_p (src, pattern)
+	    || set_of (dest, insn)
+	    || set_of (src, insn))
+	  break;
+      }
+ABORT:
+  FAIL;
+FALLTHRU:;
+})
diff --git a/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove.c b/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove.c
new file mode 100644
index 00000000000..2f0d71d12bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/xtensa/elim_GP_regmove.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fpeephole2" } */
+
+/* processed */
+double test0(double a, double b) {
+  return __builtin_copysign(a, b);
+}
+
+/* excluded: the source operands have '0' constraint.  */
+int test1(int a, int b) {
+  int c;
+  asm volatile ("" : "=a"(c) : "r"(a), "0"(b));
+  return c;
+}
+
+/* excluded: the destination operand has '&' constraint.  */
+int test2(int a) {
+  int b;
+  asm volatile ("" : "=&a"(b) : "r"(a));
+  return b;
+}
+
+/* { dg-final { scan-assembler-times "mov\t|mov.n\t" 2 } } */
-- 
2.30.2

Re: [PATCH v4] xtensa: Eliminate unnecessary general-purpose reg-reg moves

[Max Filippov]

Hi Suwa-san,

On Mon, Jan 23, 2023 at 7:43 PM Takayuki 'January June' Suwa
<jjsuwa_sys3175@yahoo.co.jp> wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
>   return __builtin_copysign(a, b);
> }
>
> test:
>         add.n   a3, a3, a3
>         extui   a5, a5, 31, 1
>         ssai    1
>                                 ;; be in the same BB
>         src     a7, a5, a3      ;; No '0' in the source constraints
>                                 ;; The destination replaced is
>                                 ;;   irrelevant to the sources if the
>                                 ;;   destination constraint has '&'
>                                 ;; No CALL insns in this span
>                                 ;; Both A3 and A7 are irrelevant to
>                                 ;;   insns in this span
>         mov.n   a3, a7          ;; An unnecessary reg-reg move
>                                 ;; A7 is not used after this
>         ret.n
>
> The last two instructions above, excluding the return instruction,
> could be done like this:
>
>         src     a3, a5, a3
>
> This symptom often occurs when handling DI/DFmode values with SImode
> instructions.  This patch solves the above problem using peephole2
> pattern.
>
> gcc/ChangeLog:
>
>         * config/xtensa/xtensa.md: New peephole2 pattern that eliminates
>         the occurrence of general-purpose register used only once and for
>         transferring intermediate value.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/xtensa/elim_GP_regmove.c: New.
> ---
>  gcc/config/xtensa/xtensa.md                   | 49 +++++++++++++++++++
>  .../gcc.target/xtensa/elim_GP_regmove.c       | 23 +++++++++
>  2 files changed, 72 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/xtensa/elim_GP_regmove.c

This change breaks windowed builds by the following ICEs:

libgcc/libgcov-interface.c: In function ‘__gcov_execlp’:
libgcc/libgcov-interface.c:263:1: error: insn does not satisfy its constraints:
 263 | }
     | ^
(insn 96 95 98 11 (set (reg/f:SI 1 sp)
       (minus:SI (reg/f:SI 1 sp)
           (reg:SI 8 a8 [85]))) "libgcc/libgcov-interface.c":253:20 4 {subsi3}
    (expr_list:REG_DEAD (reg:SI 8 a8 [85])
       (nil)))
during RTL pass: cprop_hardreg
libgcc/libgcov-interface.c:263:1: internal compiler error: in
extract_constrain_insn, at recog.cc:2692

It also introduces at least one regression in executable tests
in call0 build, I haven't tracked it down yet.

-- 
Thanks.
-- Max