Re: [v2] RISC-V: Remove masking third operand of rotate instructions

[Joern Rennecke <joern.rennecke@embecosm.com>]

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On Thu, 18 May 2023 at 16:37, Joern Rennecke <joern.rennecke@embecosm.com> wrote
in https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618928.html :
>
> This breaks building libstdc++-v3 for
> -march=rv32imafdcv_zicsr_zifencei_zba_zbb_zbc_zbs_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b
> -mabi=ilp32f .

Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
part of the subject.

2023-05-18  Joern Rennecke  <joern.rennecke@embecosm.com>

gcc/ChangeLog:
        * config/riscv/constraints.md (DsS, DsD): Restore agreement
with shiftm1 mode attribute.

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diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c448e6b37e9..44525b2da49 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -65,13 +65,13 @@
   "@internal
    31 immediate"
   (and (match_code "const_int")
-       (match_test "ival == 31")))
+       (match_test "(ival & 31) == 31")))
 
 (define_constraint "DsD"
   "@internal
    63 immediate"
   (and (match_code "const_int")
-       (match_test "ival == 63")))
+       (match_test "(ival & 63) == 63")))
 
 (define_constraint "DbS"
   "@internal"