* [PATCH v1] RISC-V: Refine the insn pattern of fsrm
@ 2023-07-04 8:41 pan2.li
2023-07-04 8:46 ` juzhe.zhong
0 siblings, 1 reply; 2+ messages in thread
From: pan2.li @ 2023-07-04 8:41 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to introduce 2 new patter of fsrm with SImode, aka:
1. fsrmsi_backup
2. fsrmsi_restore
Both patterns accept the imm and reg format, and then leverage the imm
format instead of reg when RVV floating-point static rounding mode.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_emit_mode_set): Take frm imm insn.
* config/riscv/vector.md (fsrm): Removed.
(fsrmsi_backup): New define insn.
(fsrmsi_restore): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-insert-1.c: Adjust
checker.
* gcc.target/riscv/rvv/base/float-point-frm-insert-2.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-3.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-4.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-5.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Ditto.
---
gcc/config/riscv/riscv.cc | 8 +---
gcc/config/riscv/vector.md | 38 ++++++++++---------
.../riscv/rvv/base/float-point-frm-insert-1.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-2.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-3.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-4.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-5.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-6.c | 2 +-
8 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 37f96f8a238..8342e7dd031 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7671,13 +7671,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
break;
case RISCV_FRM:
if (mode != FRM_MODE_DYN && mode != prev_mode)
- {
- rtx scaler = gen_reg_rtx (SImode);
- rtx imm = gen_int_mode (mode, SImode);
-
- emit_insn (gen_movsi (scaler, imm));
- emit_insn (gen_fsrm (scaler, scaler));
- }
+ emit_insn (gen_fsrmsi_restore (gen_int_mode (mode, SImode)));
break;
default:
gcc_unreachable ();
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 2864475b35a..13bc63a50fb 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -578,24 +578,28 @@ (define_insn "vxrmsi"
(set_attr "mode" "SI")])
;; Set FRM
-(define_insn "fsrm"
- [
- (set
- (reg:SI FRM_REGNUM)
- (unspec:SI
- [
- (match_operand:SI 0 "register_operand" "=&r")
- (match_operand:SI 1 "register_operand" "r")
- ] UNSPEC_FSRM
- )
- )
- ]
+(define_insn "fsrmsi_backup"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (reg:SI FRM_REGNUM))
+ (set (reg:SI FRM_REGNUM)
+ (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
"TARGET_VECTOR"
- "fsrm\t%0,%1"
- [
- (set_attr "type" "wrfrm")
- (set_attr "mode" "SI")
- ]
+ "@
+ fsrm\t%0,%1
+ fsrmi\t%0,%1"
+ [(set_attr "type" "wrfrm,wrfrm")
+ (set_attr "mode" "SI")]
+)
+
+(define_insn "fsrmsi_restore"
+ [(set (reg:SI FRM_REGNUM)
+ (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
+ "TARGET_VECTOR"
+ "@
+ fsrm\t%0
+ fsrmi\t%0"
+ [(set_attr "type" "wrfrm,wrfrm")
+ (set_attr "mode" "SI")]
)
;; -----------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
index 732e0305a3d..a59ffe2c65e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
@@ -28,4 +28,4 @@ test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
}
/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
index 72e5d2084b3..3254d6a40b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
@@ -11,4 +11,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
index c9e8d0a6eaf..f8679c2f716 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
@@ -11,4 +11,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
index a288e0be628..d8a15f30c5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
@@ -20,4 +20,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl,
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
index bb77a6efc62..cf603920946 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
@@ -20,4 +20,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl,
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
index 6d896e0953e..efd89ccfc3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -28,4 +28,4 @@ test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
}
/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
+/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
--
2.34.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH v1] RISC-V: Refine the insn pattern of fsrm
2023-07-04 8:41 [PATCH v1] RISC-V: Refine the insn pattern of fsrm pan2.li
@ 2023-07-04 8:46 ` juzhe.zhong
0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-07-04 8:46 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 7739 bytes --]
I prefer to defer this patch when you implementing dynamic rounding mode.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-07-04 16:41
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refine the insn pattern of fsrm
From: Pan Li <pan2.li@intel.com>
This patch would like to introduce 2 new patter of fsrm with SImode, aka:
1. fsrmsi_backup
2. fsrmsi_restore
Both patterns accept the imm and reg format, and then leverage the imm
format instead of reg when RVV floating-point static rounding mode.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_emit_mode_set): Take frm imm insn.
* config/riscv/vector.md (fsrm): Removed.
(fsrmsi_backup): New define insn.
(fsrmsi_restore): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-insert-1.c: Adjust
checker.
* gcc.target/riscv/rvv/base/float-point-frm-insert-2.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-3.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-4.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-5.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Ditto.
---
gcc/config/riscv/riscv.cc | 8 +---
gcc/config/riscv/vector.md | 38 ++++++++++---------
.../riscv/rvv/base/float-point-frm-insert-1.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-2.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-3.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-4.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-5.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-6.c | 2 +-
8 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 37f96f8a238..8342e7dd031 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7671,13 +7671,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
break;
case RISCV_FRM:
if (mode != FRM_MODE_DYN && mode != prev_mode)
- {
- rtx scaler = gen_reg_rtx (SImode);
- rtx imm = gen_int_mode (mode, SImode);
-
- emit_insn (gen_movsi (scaler, imm));
- emit_insn (gen_fsrm (scaler, scaler));
- }
+ emit_insn (gen_fsrmsi_restore (gen_int_mode (mode, SImode)));
break;
default:
gcc_unreachable ();
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 2864475b35a..13bc63a50fb 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -578,24 +578,28 @@ (define_insn "vxrmsi"
(set_attr "mode" "SI")])
;; Set FRM
-(define_insn "fsrm"
- [
- (set
- (reg:SI FRM_REGNUM)
- (unspec:SI
- [
- (match_operand:SI 0 "register_operand" "=&r")
- (match_operand:SI 1 "register_operand" "r")
- ] UNSPEC_FSRM
- )
- )
- ]
+(define_insn "fsrmsi_backup"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (reg:SI FRM_REGNUM))
+ (set (reg:SI FRM_REGNUM)
+ (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
"TARGET_VECTOR"
- "fsrm\t%0,%1"
- [
- (set_attr "type" "wrfrm")
- (set_attr "mode" "SI")
- ]
+ "@
+ fsrm\t%0,%1
+ fsrmi\t%0,%1"
+ [(set_attr "type" "wrfrm,wrfrm")
+ (set_attr "mode" "SI")]
+)
+
+(define_insn "fsrmsi_restore"
+ [(set (reg:SI FRM_REGNUM)
+ (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
+ "TARGET_VECTOR"
+ "@
+ fsrm\t%0
+ fsrmi\t%0"
+ [(set_attr "type" "wrfrm,wrfrm")
+ (set_attr "mode" "SI")]
)
;; -----------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
index 732e0305a3d..a59ffe2c65e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
@@ -28,4 +28,4 @@ test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
}
/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
index 72e5d2084b3..3254d6a40b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
@@ -11,4 +11,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
index c9e8d0a6eaf..f8679c2f716 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
@@ -11,4 +11,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
index a288e0be628..d8a15f30c5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
@@ -20,4 +20,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl,
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
index bb77a6efc62..cf603920946 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
@@ -20,4 +20,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl,
}
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
index 6d896e0953e..efd89ccfc3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -28,4 +28,4 @@ test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
}
/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
+/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
--
2.34.1
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-07-04 8:41 [PATCH v1] RISC-V: Refine the insn pattern of fsrm pan2.li
2023-07-04 8:46 ` juzhe.zhong
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