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* [PATCH] arm: Make MVE masked stores read memory operand [PR 108177]
@ 2023-01-13 16:05 Andre Simoes Dias Vieira
  2023-01-24 14:40 ` Andre Vieira (lists)
  0 siblings, 1 reply; 3+ messages in thread
From: Andre Simoes Dias Vieira @ 2023-01-13 16:05 UTC (permalink / raw)
  To: 'gcc-patches@gcc.gnu.org'; +Cc: Richard Earnshaw, Kyrylo Tkachov

[-- Attachment #1: Type: text/plain, Size: 2275 bytes --]

Hi,

This patch adds the memory operand of MVE masked stores as input operands to
mimic the 'partial' writes, to prevent erroneous write-after-write
optimizations as described in the PR.

Regression tested on arm-none-eabi for armv8.1-m.main+mve.fp. 

OK for trunk?

gcc/ChangeLog:

	PR target/108177
	* config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
	mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
	as input operand.

    gcc/testsuite/ChangeLog:

    *       gcc.target/arm/mve/pr108177-1-run.c: New test.
    *       gcc.target/arm/mve/pr108177-1.c: New test.
    *       gcc.target/arm/mve/pr108177-10-run.c: New test.
    *       gcc.target/arm/mve/pr108177-10.c: New test.
    *       gcc.target/arm/mve/pr108177-11-run.c: New test.
    *       gcc.target/arm/mve/pr108177-11.c: New test.
    *       gcc.target/arm/mve/pr108177-12-run.c: New test.
    *       gcc.target/arm/mve/pr108177-12.c: New test.
    *       gcc.target/arm/mve/pr108177-13-run.c: New test.
    *       gcc.target/arm/mve/pr108177-13.c: New test.
    *       gcc.target/arm/mve/pr108177-14-run.c: New test.
    *       gcc.target/arm/mve/pr108177-14.c: New test.
    *       gcc.target/arm/mve/pr108177-2-run.c: New test.
    *       gcc.target/arm/mve/pr108177-2.c: New test.
    *       gcc.target/arm/mve/pr108177-3-run.c: New test.
    *       gcc.target/arm/mve/pr108177-3.c: New test.
    *       gcc.target/arm/mve/pr108177-4-run.c: New test.
    *       gcc.target/arm/mve/pr108177-4.c: New test.
    *       gcc.target/arm/mve/pr108177-5-run.c: New test.
    *       gcc.target/arm/mve/pr108177-5.c: New test.
    *       gcc.target/arm/mve/pr108177-6-run.c: New test.
    *       gcc.target/arm/mve/pr108177-6.c: New test.
    *       gcc.target/arm/mve/pr108177-7-run.c: New test.
    *       gcc.target/arm/mve/pr108177-7.c: New test.
    *       gcc.target/arm/mve/pr108177-8-run.c: New test.
    *       gcc.target/arm/mve/pr108177-8.c: New test.
    *       gcc.target/arm/mve/pr108177-9-run.c: New test.
    *       gcc.target/arm/mve/pr108177-9.c: New test.
    *       gcc.target/arm/mve/pr108177-main.x: New test include.
    *       gcc.target/arm/mve/pr108177.x: New test include.

[-- Attachment #2: pr108177.patch --]
[-- Type: application/octet-stream, Size: 21017 bytes --]

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index f123edc449b8b20bfb4a15c1fb0eccdbfff1339c..2e58ad188c4b13b27f7d35ddde0f04f98b1334c6 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -7272,15 +7272,13 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
 }
   [(set_attr "length" "8")])
 
-;;
-;; [vstrbq_p_s vstrbq_p_u]
-;;
 (define_insn "mve_vstrbq_p_<supf><mode>"
   [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRBQ))
-  ]
+	(unspec:<MVE_B_ELEM>
+	 [(match_operand:MVE_2 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRBQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
@@ -8079,10 +8077,11 @@ (define_insn "mve_vstrhq_fv8hf"
 ;;
 (define_insn "mve_vstrhq_p_fv8hf"
   [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
-	(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
-		      (match_operand:V8BI 2 "vpr_register_operand" "Up")]
-	 VSTRHQ_F))
-  ]
+	(unspec:V8HI
+	 [(match_operand:V8HF 1 "s_register_operand" "w")
+	  (match_operand:V8BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRHQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8099,8 +8098,10 @@ (define_insn "mve_vstrhq_p_fv8hf"
 ;;
 (define_insn "mve_vstrhq_p_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
+	(unspec:<MVE_H_ELEM>
+	 [(match_operand:MVE_6 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
 	 VSTRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -8278,10 +8279,11 @@ (define_insn "mve_vstrwq_fv4sf"
 ;;
 (define_insn "mve_vstrwq_p_fv4sf"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
-		      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRWQ_F))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SF 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8298,10 +8300,11 @@ (define_insn "mve_vstrwq_p_fv4sf"
 ;;
 (define_insn "mve_vstrwq_p_<supf>v4si"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4BI 2 "vpr_register_operand" "Up")]
-	 VSTRWQ))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SI 1 "s_register_operand" "w")
+	  (match_operand:V4BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..ca092df9802153bc4b21e919f91f4bacfe23b6de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-1.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
new file mode 100644
index 0000000000000000000000000000000000000000..2d42062bc8e879233b2e7974ea93c8277128aaac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint8x16_t
+#define INTRINSIC vstrbq_u8
+#define INTRINSIC_P vstrbq_p_u8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..0a58b8f7fdfed12816c37747b5d60f2a07d44a57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-10.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
new file mode 100644
index 0000000000000000000000000000000000000000..4db594f588f9f299a6c22df5de686aa68f612ba9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrhq_s32
+#define INTRINSIC_P vstrhq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..9f568eacf346a08a22d82d4caac5e0ef465ddfc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-11.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
new file mode 100644
index 0000000000000000000000000000000000000000..329fcb33eebc2df9d047f59c14259221a1cc2a6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrwq_u32
+#define INTRINSIC_P vstrwq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..8e946a29795248da21ff993b8b29fe4e60cda16b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-12.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
new file mode 100644
index 0000000000000000000000000000000000000000..3f7c5b2a4c12e27d12b60e6c6d0157dde3a03b86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrwq_s32
+#define INTRINSIC_P vstrwq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..2e731ee3824bb1c29b418f09b384da1a4899471e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-13.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
new file mode 100644
index 0000000000000000000000000000000000000000..2f82228d8f6b7f5fe12ce51d49079dc27eb186f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE float16x8_t
+#define INTRINSIC vstrhq_f16
+#define INTRINSIC_P vstrhq_p_f16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..3cebcf5bbcd6f9f0b01fc7b0a71a1ffb0442d2f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-14.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
new file mode 100644
index 0000000000000000000000000000000000000000..ba6196b799490f8897e51670bbe740161ff6a613
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE float32x4_t
+#define INTRINSIC vstrwq_f32
+#define INTRINSIC_P vstrwq_p_f32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..03750c9c7a1eea9ac3669b69b06cf5a40ca5d4a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-2.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..52c8d87ccc8c776de3bdedc832dc7967dae3b505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE int8x16_t
+#define INTRINSIC vstrbq_s8
+#define INTRINSIC_P vstrbq_p_s8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..bab08e042d42eb19a001209d5ac1613458d1713a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-3.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
new file mode 100644
index 0000000000000000000000000000000000000000..ac89e7ea883f9ed638a1092712d34da6d00b3c27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrbq_u16
+#define INTRINSIC_P vstrbq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..cff62c75dd583ae43eda259e5308a81c250125d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-4.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
new file mode 100644
index 0000000000000000000000000000000000000000..dc4f7ddab073215a4f8cbb61adff573b4eef0d60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrbq_s16
+#define INTRINSIC_P vstrbq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..7211828ceeb54b1d68f27f248ddfcf00bbac1487
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-5.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
new file mode 100644
index 0000000000000000000000000000000000000000..d1dfd328d660d38f62c188ee8e61aefd195ef929
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrbq_u32
+#define INTRINSIC_P vstrbq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..4e7d108cd81c380183ab21505bc2e984f49f0aea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-6.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
new file mode 100644
index 0000000000000000000000000000000000000000..fa70dde9eeb312867473eed036df2e7f502eaad1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrbq_s32
+#define INTRINSIC_P vstrbq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..94c492ed96b326063b01598ec30622d9da62d761
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-7.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
new file mode 100644
index 0000000000000000000000000000000000000000..73cd8605171d31d20f25b6953563e2e2350ce0e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrhq_u16
+#define INTRINSIC_P vstrhq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c34045f31d89ce4558cb37e34a7cae369086f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-8.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
new file mode 100644
index 0000000000000000000000000000000000000000..187c2b3f4ce4b839536acc74d1dfb4801fd10078
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrhq_s16
+#define INTRINSIC_P vstrhq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..967cf7f19928bcdd9f0ac03e851aefd09da255f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-9.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
new file mode 100644
index 0000000000000000000000000000000000000000..caecd18a8810c6853cf642fd982bf35eef2db1ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrhq_u32
+#define INTRINSIC_P vstrhq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
new file mode 100644
index 0000000000000000000000000000000000000000..f5f965fb698ea0279da652bf5795f9b222f7f62c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
@@ -0,0 +1,31 @@
+#include <arm_mve.h>
+extern void abort (void);
+
+__attribute__ ((noipa)) void
+write_expected (uint32x4_t v, void *a)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC (a, _v);
+}
+
+void test (uint32x4_t, void *, mve_pred16_t, mve_pred16_t);
+
+int main(void)
+{
+  uint32x4_t v = {0, 1, 2, 3};
+  uint32_t actual[] = {0, 0, 0, 0};
+  uint32_t expected[] = {0, 0, 0, 0};
+
+  write_expected (v, &(expected[0]));
+
+  mve_pred16_t p1 = 0xff00;
+  mve_pred16_t p2 = 0x00ff;
+
+  test (v, (void *)&actual[0], p1, p2);
+
+  if (__builtin_memcmp (&actual[0], &expected[0], 16) != 0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177.x b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
new file mode 100644
index 0000000000000000000000000000000000000000..019ef54eae7a3b2bc11bc6fd4bf82e4355ad1088
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
@@ -0,0 +1,9 @@
+#include "pr108177-main.x"
+
+__attribute__ ((noipa)) void
+test (uint32x4_t v, void *a, mve_pred16_t p1, mve_pred16_t p2)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC_P (a, _v, p1);
+  INTRINSIC_P (a, _v, p2);
+}

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] arm: Make MVE masked stores read memory operand [PR 108177]
  2023-01-13 16:05 [PATCH] arm: Make MVE masked stores read memory operand [PR 108177] Andre Simoes Dias Vieira
@ 2023-01-24 14:40 ` Andre Vieira (lists)
  2023-01-24 14:57   ` Kyrylo Tkachov
  0 siblings, 1 reply; 3+ messages in thread
From: Andre Vieira (lists) @ 2023-01-24 14:40 UTC (permalink / raw)
  To: 'gcc-patches@gcc.gnu.org'; +Cc: Richard Earnshaw, Kyrylo Tkachov

[-- Attachment #1: Type: text/plain, Size: 2485 bytes --]

ping. (reattaching patch in the hopes patchwork picks it up).

On 13/01/2023 16:05, Andre Simoes Dias Vieira via Gcc-patches wrote:
> Hi,
> 
> This patch adds the memory operand of MVE masked stores as input operands to
> mimic the 'partial' writes, to prevent erroneous write-after-write
> optimizations as described in the PR.
> 
> Regression tested on arm-none-eabi for armv8.1-m.main+mve.fp.
> 
> OK for trunk?
> 
> gcc/ChangeLog:
> 
> 	PR target/108177
> 	* config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
> 	mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
> 	as input operand.
> 
>      gcc/testsuite/ChangeLog:
> 
>      *       gcc.target/arm/mve/pr108177-1-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-1.c: New test.
>      *       gcc.target/arm/mve/pr108177-10-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-10.c: New test.
>      *       gcc.target/arm/mve/pr108177-11-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-11.c: New test.
>      *       gcc.target/arm/mve/pr108177-12-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-12.c: New test.
>      *       gcc.target/arm/mve/pr108177-13-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-13.c: New test.
>      *       gcc.target/arm/mve/pr108177-14-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-14.c: New test.
>      *       gcc.target/arm/mve/pr108177-2-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-2.c: New test.
>      *       gcc.target/arm/mve/pr108177-3-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-3.c: New test.
>      *       gcc.target/arm/mve/pr108177-4-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-4.c: New test.
>      *       gcc.target/arm/mve/pr108177-5-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-5.c: New test.
>      *       gcc.target/arm/mve/pr108177-6-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-6.c: New test.
>      *       gcc.target/arm/mve/pr108177-7-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-7.c: New test.
>      *       gcc.target/arm/mve/pr108177-8-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-8.c: New test.
>      *       gcc.target/arm/mve/pr108177-9-run.c: New test.
>      *       gcc.target/arm/mve/pr108177-9.c: New test.
>      *       gcc.target/arm/mve/pr108177-main.x: New test include.
>      *       gcc.target/arm/mve/pr108177.x: New test include.

[-- Attachment #2: pr108177.patch --]
[-- Type: text/plain, Size: 21017 bytes --]

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index f123edc449b8b20bfb4a15c1fb0eccdbfff1339c..2e58ad188c4b13b27f7d35ddde0f04f98b1334c6 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -7272,15 +7272,13 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
 }
   [(set_attr "length" "8")])
 
-;;
-;; [vstrbq_p_s vstrbq_p_u]
-;;
 (define_insn "mve_vstrbq_p_<supf><mode>"
   [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRBQ))
-  ]
+	(unspec:<MVE_B_ELEM>
+	 [(match_operand:MVE_2 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRBQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
@@ -8079,10 +8077,11 @@ (define_insn "mve_vstrhq_fv8hf"
 ;;
 (define_insn "mve_vstrhq_p_fv8hf"
   [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
-	(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
-		      (match_operand:V8BI 2 "vpr_register_operand" "Up")]
-	 VSTRHQ_F))
-  ]
+	(unspec:V8HI
+	 [(match_operand:V8HF 1 "s_register_operand" "w")
+	  (match_operand:V8BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRHQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8099,8 +8098,10 @@ (define_insn "mve_vstrhq_p_fv8hf"
 ;;
 (define_insn "mve_vstrhq_p_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
+	(unspec:<MVE_H_ELEM>
+	 [(match_operand:MVE_6 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
 	 VSTRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -8278,10 +8279,11 @@ (define_insn "mve_vstrwq_fv4sf"
 ;;
 (define_insn "mve_vstrwq_p_fv4sf"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
-		      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRWQ_F))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SF 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8298,10 +8300,11 @@ (define_insn "mve_vstrwq_p_fv4sf"
 ;;
 (define_insn "mve_vstrwq_p_<supf>v4si"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4BI 2 "vpr_register_operand" "Up")]
-	 VSTRWQ))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SI 1 "s_register_operand" "w")
+	  (match_operand:V4BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..ca092df9802153bc4b21e919f91f4bacfe23b6de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-1.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
new file mode 100644
index 0000000000000000000000000000000000000000..2d42062bc8e879233b2e7974ea93c8277128aaac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint8x16_t
+#define INTRINSIC vstrbq_u8
+#define INTRINSIC_P vstrbq_p_u8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..0a58b8f7fdfed12816c37747b5d60f2a07d44a57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-10.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
new file mode 100644
index 0000000000000000000000000000000000000000..4db594f588f9f299a6c22df5de686aa68f612ba9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrhq_s32
+#define INTRINSIC_P vstrhq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..9f568eacf346a08a22d82d4caac5e0ef465ddfc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-11.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
new file mode 100644
index 0000000000000000000000000000000000000000..329fcb33eebc2df9d047f59c14259221a1cc2a6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrwq_u32
+#define INTRINSIC_P vstrwq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..8e946a29795248da21ff993b8b29fe4e60cda16b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-12.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
new file mode 100644
index 0000000000000000000000000000000000000000..3f7c5b2a4c12e27d12b60e6c6d0157dde3a03b86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrwq_s32
+#define INTRINSIC_P vstrwq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..2e731ee3824bb1c29b418f09b384da1a4899471e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-13.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
new file mode 100644
index 0000000000000000000000000000000000000000..2f82228d8f6b7f5fe12ce51d49079dc27eb186f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE float16x8_t
+#define INTRINSIC vstrhq_f16
+#define INTRINSIC_P vstrhq_p_f16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..3cebcf5bbcd6f9f0b01fc7b0a71a1ffb0442d2f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-14.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
new file mode 100644
index 0000000000000000000000000000000000000000..ba6196b799490f8897e51670bbe740161ff6a613
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE float32x4_t
+#define INTRINSIC vstrwq_f32
+#define INTRINSIC_P vstrwq_p_f32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..03750c9c7a1eea9ac3669b69b06cf5a40ca5d4a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-2.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..52c8d87ccc8c776de3bdedc832dc7967dae3b505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE int8x16_t
+#define INTRINSIC vstrbq_s8
+#define INTRINSIC_P vstrbq_p_s8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..bab08e042d42eb19a001209d5ac1613458d1713a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-3.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
new file mode 100644
index 0000000000000000000000000000000000000000..ac89e7ea883f9ed638a1092712d34da6d00b3c27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrbq_u16
+#define INTRINSIC_P vstrbq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..cff62c75dd583ae43eda259e5308a81c250125d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-4.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
new file mode 100644
index 0000000000000000000000000000000000000000..dc4f7ddab073215a4f8cbb61adff573b4eef0d60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrbq_s16
+#define INTRINSIC_P vstrbq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..7211828ceeb54b1d68f27f248ddfcf00bbac1487
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-5.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
new file mode 100644
index 0000000000000000000000000000000000000000..d1dfd328d660d38f62c188ee8e61aefd195ef929
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrbq_u32
+#define INTRINSIC_P vstrbq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..4e7d108cd81c380183ab21505bc2e984f49f0aea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-6.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
new file mode 100644
index 0000000000000000000000000000000000000000..fa70dde9eeb312867473eed036df2e7f502eaad1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrbq_s32
+#define INTRINSIC_P vstrbq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..94c492ed96b326063b01598ec30622d9da62d761
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-7.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
new file mode 100644
index 0000000000000000000000000000000000000000..73cd8605171d31d20f25b6953563e2e2350ce0e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrhq_u16
+#define INTRINSIC_P vstrhq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c34045f31d89ce4558cb37e34a7cae369086f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-8.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
new file mode 100644
index 0000000000000000000000000000000000000000..187c2b3f4ce4b839536acc74d1dfb4801fd10078
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrhq_s16
+#define INTRINSIC_P vstrhq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
new file mode 100644
index 0000000000000000000000000000000000000000..967cf7f19928bcdd9f0ac03e851aefd09da255f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-9.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
new file mode 100644
index 0000000000000000000000000000000000000000..caecd18a8810c6853cf642fd982bf35eef2db1ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrhq_u32
+#define INTRINSIC_P vstrhq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
new file mode 100644
index 0000000000000000000000000000000000000000..f5f965fb698ea0279da652bf5795f9b222f7f62c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
@@ -0,0 +1,31 @@
+#include <arm_mve.h>
+extern void abort (void);
+
+__attribute__ ((noipa)) void
+write_expected (uint32x4_t v, void *a)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC (a, _v);
+}
+
+void test (uint32x4_t, void *, mve_pred16_t, mve_pred16_t);
+
+int main(void)
+{
+  uint32x4_t v = {0, 1, 2, 3};
+  uint32_t actual[] = {0, 0, 0, 0};
+  uint32_t expected[] = {0, 0, 0, 0};
+
+  write_expected (v, &(expected[0]));
+
+  mve_pred16_t p1 = 0xff00;
+  mve_pred16_t p2 = 0x00ff;
+
+  test (v, (void *)&actual[0], p1, p2);
+
+  if (__builtin_memcmp (&actual[0], &expected[0], 16) != 0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177.x b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
new file mode 100644
index 0000000000000000000000000000000000000000..019ef54eae7a3b2bc11bc6fd4bf82e4355ad1088
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
@@ -0,0 +1,9 @@
+#include "pr108177-main.x"
+
+__attribute__ ((noipa)) void
+test (uint32x4_t v, void *a, mve_pred16_t p1, mve_pred16_t p2)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC_P (a, _v, p1);
+  INTRINSIC_P (a, _v, p2);
+}

^ permalink raw reply	[flat|nested] 3+ messages in thread
* RE: [PATCH] arm: Make MVE masked stores read memory operand [PR 108177]
  2023-01-24 14:40 ` Andre Vieira (lists)
@ 2023-01-24 14:57   ` Kyrylo Tkachov
  0 siblings, 0 replies; 3+ messages in thread
From: Kyrylo Tkachov @ 2023-01-24 14:57 UTC (permalink / raw)
  To: Andre Simoes Dias Vieira, 'gcc-patches@gcc.gnu.org'
  Cc: Richard Earnshaw



> -----Original Message-----
> From: Andre Vieira (lists) <andre.simoesdiasvieira@arm.com>
> Sent: Tuesday, January 24, 2023 2:40 PM
> To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>
> Subject: Re: [PATCH] arm: Make MVE masked stores read memory operand
> [PR 108177]
> 
> ping. (reattaching patch in the hopes patchwork picks it up).
> 
> On 13/01/2023 16:05, Andre Simoes Dias Vieira via Gcc-patches wrote:
> > Hi,
> >
> > This patch adds the memory operand of MVE masked stores as input
> operands to
> > mimic the 'partial' writes, to prevent erroneous write-after-write
> > optimizations as described in the PR.
> >
> > Regression tested on arm-none-eabi for armv8.1-m.main+mve.fp.
> >
> > OK for trunk?

Ok.
Thanks,
Kyrill

> >
> > gcc/ChangeLog:
> >
> > 	PR target/108177
> > 	* config/arm/mve.md (mve_vstrbq_p_<supf><mode>,
> mve_vstrhq_p_fv8hf,
> > 	mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add
> memory operand
> > 	as input operand.
> >
> >      gcc/testsuite/ChangeLog:
> >
> >      *       gcc.target/arm/mve/pr108177-1-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-1.c: New test.
> >      *       gcc.target/arm/mve/pr108177-10-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-10.c: New test.
> >      *       gcc.target/arm/mve/pr108177-11-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-11.c: New test.
> >      *       gcc.target/arm/mve/pr108177-12-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-12.c: New test.
> >      *       gcc.target/arm/mve/pr108177-13-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-13.c: New test.
> >      *       gcc.target/arm/mve/pr108177-14-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-14.c: New test.
> >      *       gcc.target/arm/mve/pr108177-2-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-2.c: New test.
> >      *       gcc.target/arm/mve/pr108177-3-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-3.c: New test.
> >      *       gcc.target/arm/mve/pr108177-4-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-4.c: New test.
> >      *       gcc.target/arm/mve/pr108177-5-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-5.c: New test.
> >      *       gcc.target/arm/mve/pr108177-6-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-6.c: New test.
> >      *       gcc.target/arm/mve/pr108177-7-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-7.c: New test.
> >      *       gcc.target/arm/mve/pr108177-8-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-8.c: New test.
> >      *       gcc.target/arm/mve/pr108177-9-run.c: New test.
> >      *       gcc.target/arm/mve/pr108177-9.c: New test.
> >      *       gcc.target/arm/mve/pr108177-main.x: New test include.
> >      *       gcc.target/arm/mve/pr108177.x: New test include.

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-01-24 14:57 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-13 16:05 [PATCH] arm: Make MVE masked stores read memory operand [PR 108177] Andre Simoes Dias Vieira
2023-01-24 14:40 ` Andre Vieira (lists)
2023-01-24 14:57   ` Kyrylo Tkachov

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