From: Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: "law@redhat.com" <law@redhat.com>,
Prafulla Thakare <Prafulla.Thakare@kpitcummins.com>
Subject: [Patch : H8300] Bug fix for bit insn and minor tweaks to insns
Date: Thu, 09 Jun 2011 07:40:00 -0000 [thread overview]
Message-ID: <F56EA673D3E56E48804FE2B0D23EFD2D22FC98AC8E@KCINPUNHJCMS01.kpit.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 856 bytes --]
Hi,
The following patch fixes an ICE that is generated when the compiler tries
to perform bit manipulation for logical operations when the source and
destination address does not match. The testcase is also included in the
patch(gcc.dg).
The additional condition in the insn takes care of the ICE which occurs at '-O1'.
The other insn's are reordered to give preference to bit instructions using existing
constraints.
Ok to apply?
Thanks & Regards,
Kaushik Phatak
www.kpitgnutools.com
2011-06-09 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
* config/h8300/h8300.md (bsetqi_msx, bclrqi_msx, bnotqi_msx): Added
condition to disallow non-identical memory locations.
(*andqi3_2, andqi3_1, iorqi3_1, xorqi3_1): Reorder insn to give
preference to bit manipulation instructions.
* gcc.dg/h8300-bit-insn-ice2.2: New testcase.
[-- Attachment #2: h8_bit.diff --]
[-- Type: application/octet-stream, Size: 5423 bytes --]
Index: gcc/config/h8300/h8300.md
===================================================================
--- gcc/config/h8300/h8300.md (revision 174833)
+++ gcc/config/h8300/h8300.md (working copy)
@@ -1767,7 +1767,8 @@
[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
(and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
(match_operand:QI 2 "single_zero_operand" "Y0")))]
- "TARGET_H8300SX"
+ "TARGET_H8300SX
+ && INTVAL (XEXP (operands[0], 0)) == INTVAL (XEXP (operands[1], 0))"
"bclr\\t%W2,%0"
[(set_attr "length" "8")])
@@ -1800,29 +1801,31 @@
"TARGET_H8300SX"
"bclr\\t%W2,%0"
[(set_attr "length" "8")])
+
(define_insn "*andqi3_2"
- [(set (match_operand:QI 0 "bit_operand" "=rQ,r")
- (and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
- (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
+ [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
+ (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
+ (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
"TARGET_H8300SX"
"@
- and %X2,%X0
- bfld %2,%1,%R0"
- [(set_attr "length" "*,8")
- (set_attr "length_table" "logicb,*")
- (set_attr "cc" "set_znv,none_0hit")])
+ bclr\\t %W2,%R0
+ and %X2,%X0
+ bfld %2,%1,%R0"
+ [(set_attr "length" "8,*,8")
+ (set_attr "length_table" "*,logicb,*")
+ (set_attr "cc" "none_0hit,set_znv,none_0hit")])
(define_insn "andqi3_1"
- [(set (match_operand:QI 0 "bit_operand" "=r,U")
+ [(set (match_operand:QI 0 "bit_operand" "=U,r")
(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "h8300_src_operand" "rn,n")))]
+ (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
"register_operand (operands[0], QImode)
|| single_zero_operand (operands[2], QImode)"
"@
- and %X2,%X0
- bclr %W2,%R0"
+ bclr %W2,%R0
+ and %X2,%X0"
[(set_attr "length" "2,8")
- (set_attr "cc" "set_znv,none_0hit")])
+ (set_attr "cc" "none_0hit,set_znv")])
(define_expand "andqi3"
[(set (match_operand:QI 0 "register_operand" "")
@@ -1903,11 +1906,13 @@
;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------
+
(define_insn "bsetqi_msx"
[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
(ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
(match_operand:QI 2 "single_one_operand" "Y2")))]
- "TARGET_H8300SX"
+ "TARGET_H8300SX
+ && INTVAL (XEXP (operands[0], 0)) == INTVAL (XEXP (operands[1], 0))"
"bset\\t%V2,%0"
[(set_attr "length" "8")])
@@ -1942,18 +1947,19 @@
[(set_attr "length" "8")])
(define_insn "iorqi3_1"
- [(set (match_operand:QI 0 "bit_operand" "=rQ,U")
+ [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
+ (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
"TARGET_H8300SX || register_operand (operands[0], QImode)
|| single_one_operand (operands[2], QImode)"
"@
- or\\t%X2,%X0
- bset\\t%V2,%R0"
- [(set_attr "length" "*,8")
- (set_attr "length_table" "logicb,*")
- (set_attr "cc" "set_znv,none_0hit")])
+ bset\\t%V2,%R0
+ or\\t%X2,%X0"
+ [(set_attr "length" "8,*")
+ (set_attr "length_table" "*,logicb")
+ (set_attr "cc" "none_0hit,set_znv")])
+
(define_expand "iorqi3"
[(set (match_operand:QI 0 "register_operand" "")
(ior:QI (match_operand:QI 1 "register_operand" "")
@@ -1982,7 +1988,8 @@
[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
(xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
(match_operand:QI 2 "single_one_operand" "Y2")))]
- "TARGET_H8300SX"
+ "TARGET_H8300SX
+ && INTVAL (XEXP (operands[0], 0)) == INTVAL (XEXP (operands[1], 0))"
"bnot\\t%V2,%0"
[(set_attr "length" "8")])
@@ -2017,18 +2024,19 @@
[(set_attr "length" "8")])
(define_insn "xorqi3_1"
- [(set (match_operand:QI 0 "bit_operand" "=r,U")
+ [(set (match_operand:QI 0 "bit_operand" "=U,r")
(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
+ (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
"TARGET_H8300SX || register_operand (operands[0], QImode)
|| single_one_operand (operands[2], QImode)"
"@
- xor\\t%X2,%X0
- bnot\\t%V2,%R0"
- [(set_attr "length" "*,8")
- (set_attr "length_table" "logicb,*")
- (set_attr "cc" "set_znv,none_0hit")])
+ bnot\\t%V2,%R0
+ xor\\t%X2,%X0"
+ [(set_attr "length" "8,*")
+ (set_attr "length_table" "*,logicb")
+ (set_attr "cc" "none_0hit,set_znv")])
+
(define_expand "xorqi3"
[(set (match_operand:QI 0 "register_operand" "")
(xor:QI (match_operand:QI 1 "register_operand" "")
Index: gcc/testsuite/gcc.dg/h8300-bit-insn-ice2.c
===================================================================
--- gcc/testsuite/gcc.dg/h8300-bit-insn-ice2.c (revision 0)
+++ gcc/testsuite/gcc.dg/h8300-bit-insn-ice2.c (revision 0)
@@ -0,0 +1,15 @@
+/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */
+/* { dg-options "-O2" } */
+/* ICE for bit instruction generation using 16-bit const */
+
+#define MSTPCRA (*(volatile unsigned char*)0xFFFFC9)
+#define MSTPCRA2 (*(volatile unsigned char*)0xFFFDC8)
+
+int
+main (void)
+{
+ MSTPCRA = MSTPCRA2 & ~0x01;
+ MSTPCRA = MSTPCRA2 ^ ~0xFE;
+ MSTPCRA = MSTPCRA2 | ~0xFE;
+ return 0;
+}
next reply other threads:[~2011-06-09 7:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-09 7:40 Kaushik Phatak [this message]
2011-06-10 18:37 ` Jeff Law
2011-06-13 10:57 ` Kaushik Phatak
2011-06-13 15:24 ` H.J. Lu
2011-06-13 13:16 ` Eric Botcazou
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