* [PATCH] RISC-V: Add more SLP tests
@ 2023-06-13 9:14 juzhe.zhong
2023-06-13 10:08 ` Robin Dapp
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-06-13 9:14 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc,
Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test.
* gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: New test.
---
.../riscv/rvv/autovec/partial/slp-10.c | 30 ++++++++++++++++++
.../riscv/rvv/autovec/partial/slp-11.c | 31 +++++++++++++++++++
.../riscv/rvv/autovec/partial/slp_run-10.c | 30 ++++++++++++++++++
.../riscv/rvv/autovec/partial/slp_run-11.c | 30 ++++++++++++++++++
4 files changed, 121 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
new file mode 100644
index 00000000000..b33e85c5be2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 2] += 10; \
+ a[i * 2 + 1] += 17; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump-times "{ 10, 17, ... }" 8 "optimized" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
new file mode 100644
index 00000000000..c62eced99f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+#define VEC_PERM(TYPE) \
+ TYPE __attribute__ ((noinline, noclone)) \
+ vec_slp_##TYPE (TYPE *restrict a, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ a[i * 4] += 41; \
+ a[i * 4 + 1] += 25; \
+ a[i * 4 + 2] += 31; \
+ a[i * 4 + 3] += 62; \
+ } \
+ }
+
+#define TEST_ALL(T) \
+ T (int8_t) \
+ T (uint8_t) \
+ T (int16_t) \
+ T (uint16_t) \
+ T (int32_t) \
+ T (uint32_t) \
+ T (int64_t) \
+ T (uint64_t)
+
+TEST_ALL (VEC_PERM)
+
+/* { dg-final { scan-tree-dump "{ 41, 25, 31, 62, ... }" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
new file mode 100644
index 00000000000..24ffc9656b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-10.c"
+
+#define N (103 * 2)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[2] = { 10, 17 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 2); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 2]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
new file mode 100644
index 00000000000..3e5fceb7d58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "slp-11.c"
+
+#define N (77 * 4)
+
+#define HARNESS(TYPE) \
+ { \
+ TYPE a[N], b[4] = { 41, 25, 31, 62 }; \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ a[i] = i * 2 + i % 5; \
+ asm volatile ("" ::: "memory"); \
+ } \
+ vec_slp_##TYPE (a, N / 4); \
+ for (unsigned int i = 0; i < N; ++i) \
+ { \
+ TYPE orig = i * 2 + i % 5; \
+ TYPE expected = orig + b[i % 4]; \
+ if (a[i] != expected) \
+ __builtin_abort (); \
+ } \
+ }
+
+int __attribute__ ((optimize (1)))
+main (void)
+{
+ TEST_ALL (HARNESS)
+}
--
2.36.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Add more SLP tests
2023-06-13 9:14 [PATCH] RISC-V: Add more SLP tests juzhe.zhong
@ 2023-06-13 10:08 ` Robin Dapp
2023-06-13 10:14 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: Robin Dapp @ 2023-06-13 10:08 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches
Cc: rdapp.gcc, kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw
Hi Juzhe,
as the tests are mostly directly from aarch64's testsuite I would
advise comments on where they were taken from as well as a TODO that
they should become common tests for a specific target selector
(vect_scalable_supported or something).
How about some assembly checks for the non-run tests?
Regards
Robin
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Re: [PATCH] RISC-V: Add more SLP tests
2023-06-13 10:08 ` Robin Dapp
@ 2023-06-13 10:14 ` juzhe.zhong
0 siblings, 0 replies; 3+ messages in thread
From: juzhe.zhong @ 2023-06-13 10:14 UTC (permalink / raw)
To: Robin Dapp, gcc-patches
Cc: Robin Dapp, kito.cheng, Kito.cheng, palmer, palmer, jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 1153 bytes --]
>> as the tests are mostly directly from aarch64's testsuite I would
>> advise comments on where they were taken from as well as a TODO that
>> they should become common tests for a specific target selector
>> (vect_scalable_supported or something).
Ok.
>> (How about some assembly checks for the non-run tests?
No, I tried. I can't add assembly check in the tests since we are SLP using different LMUL.
Different LMUL will end up with different SLP style and their instructions are quite different.
Unless we can have assembly check with predicate recognizing LMUL=M1/M2/M4/M8
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2023-06-13 18:08
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add more SLP tests
Hi Juzhe,
as the tests are mostly directly from aarch64's testsuite I would
advise comments on where they were taken from as well as a TODO that
they should become common tests for a specific target selector
(vect_scalable_supported or something).
How about some assembly checks for the non-run tests?
Regards
Robin
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-06-13 10:14 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-13 9:14 [PATCH] RISC-V: Add more SLP tests juzhe.zhong
2023-06-13 10:08 ` Robin Dapp
2023-06-13 10:14 ` juzhe.zhong
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).