* [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32
@ 2023-10-28 2:05 Juzhe-Zhong
2023-10-30 7:41 ` Robin Dapp
0 siblings, 1 reply; 3+ messages in thread
From: Juzhe-Zhong @ 2023-10-28 2:05 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, kito.cheng, rdapp.gcc, jeffreyalaw, Juzhe-Zhong
sew64_scalar_helper is handling SEW64 vx instruction pattern on RV32 system.
According to RVV ISA, we can directly use vx instruction of SEW64 on RV32 system
since RV32 GR reg is 32bit.
Consider this following case:
vsetvl e64m1
vadd.vx v,v,x
will be transform by sew64_scalar_helper:
vsetvl e64m1
sw
sw
vlse v
vadd.vv
This bug is reported by Robin.
(insn 143 179 230 9 (set (reg:SI 15 a5 [234])
(unspec:SI [
(const_int 64 [0x40])
] UNSPEC_VLMAX)) 751 {vlmax_avlsi}
(expr_list:REG_EQUIV (unspec:SI [
(const_int 64 [0x40])
] UNSPEC_VLMAX)
(nil)))
(insn 230 143 78 9 (parallel [
(set (reg:SI 66 vl)
(unspec:SI [
(reg:SI 15 a5 [234])
(const_int 64 [0x40])
(const_int 0 [0])
] UNSPEC_VSETVL))
(set (reg:SI 67 vtype)
(unspec:SI [
(const_int 64 [0x40])
(const_int 0 [0])
(const_int 1 [0x1]) repeated x2
] UNSPEC_VSETVL))
]) "bug.c":14:14 discrim 1 1469 {vsetvl_discard_resultsi}
(nil))
(insn 78 230 84 9 (set (reg:RVVM1DI 102 v6 [203])
(if_then_else:RVVM1DI (unspec:RVVMF64BI [
(const_vector:RVVMF64BI repeat [
(const_int 1 [0x1])
])
(const_int 0 [0])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(vec_duplicate:RVVM1DI (mem/u/c:DI (reg/f:SI 29 t4 [230]) [0 S8 A64]))
(unspec:RVVM1DI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "bug.c":14:14 discrim 1 1872 {*pred_broadcastrvvm1di}
(expr_list:REG_DEAD (reg/f:SI 29 t4 [230])
(nil)))
The root cause of this is because we missed VLMAX handling since the codes was invented
long time ago (Callers always intrinsics codes, no VLMAX situation).
Now, all following bugs are fixed after this patch:
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
gcc/ChangeLog:
* config/riscv/riscv-protos.h (sew64_scalar_helper): Fix bug.
* config/riscv/riscv-v.cc (sew64_scalar_helper): Ditto.
* config/riscv/vector.md: Ditto.
---
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv-v.cc | 8 +++--
gcc/config/riscv/vector.md | 54 ++++++++++++++++++++++-----------
3 files changed, 43 insertions(+), 21 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 2926d5d50d5..150b61bb5b5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -490,7 +490,7 @@ void expand_vec_lceil (rtx, rtx, machine_mode, machine_mode);
void expand_vec_lfloor (rtx, rtx, machine_mode, machine_mode);
#endif
bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
- bool, void (*)(rtx *, rtx));
+ bool, void (*)(rtx *, rtx), enum avl_type);
rtx gen_scalar_move_mask (machine_mode);
rtx gen_no_side_effects_vsetvl_rtx (machine_mode, rtx, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 53991cc1090..ee631404b44 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1641,7 +1641,7 @@ has_vi_variant_p (rtx_code code, rtx x)
bool
sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl,
machine_mode vector_mode, bool has_vi_variant_p,
- void (*emit_vector_func) (rtx *, rtx))
+ void (*emit_vector_func) (rtx *, rtx), enum avl_type type)
{
machine_mode scalar_mode = GET_MODE_INNER (vector_mode);
if (has_vi_variant_p)
@@ -1671,7 +1671,11 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl,
rtx tmp = gen_reg_rtx (vector_mode);
rtx ops[] = {tmp, *scalar_op};
- emit_nonvlmax_insn (code_for_pred_broadcast (vector_mode), UNARY_OP, ops, vl);
+ if (type == VLMAX)
+ emit_vlmax_insn (code_for_pred_broadcast (vector_mode), UNARY_OP, ops);
+ else
+ emit_nonvlmax_insn (code_for_pred_broadcast (vector_mode), UNARY_OP, ops,
+ vl);
emit_vector_func (operands, tmp);
return true;
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cea3dbf37a6..c4c136cb5d2 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1779,7 +1779,8 @@
emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
operands[2], boardcast_scalar, operands[4], operands[5],
operands[6], operands[7]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[7])))
DONE;
})
@@ -2537,7 +2538,8 @@
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
operands[2], operands[3], boardcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -2612,7 +2614,8 @@
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
operands[2], operands[3], boardcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -2687,7 +2690,8 @@
emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
operands[2], boardcast_scalar, operands[3], operands[5],
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -2804,7 +2808,8 @@
emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
operands[2], operands[3], boardcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -2978,7 +2983,8 @@
emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
operands[2], boardcast_scalar, operands[4], operands[5],
operands[6], operands[7]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[7])))
DONE;
})
@@ -3061,7 +3067,8 @@
emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
operands[2], boardcast_scalar, operands[4], operands[5],
operands[6], operands[7]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[7])))
DONE;
})
@@ -3218,7 +3225,8 @@
[] (rtx *operands, rtx boardcast_scalar) {
emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
boardcast_scalar, operands[3], operands[4], operands[5]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[5])))
DONE;
})
@@ -3287,7 +3295,8 @@
[] (rtx *operands, rtx boardcast_scalar) {
emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
boardcast_scalar, operands[3], operands[4], operands[5]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[5])))
DONE;
})
@@ -3429,7 +3438,8 @@
[] (rtx *operands, rtx boardcast_scalar) {
emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
boardcast_scalar, operands[3], operands[4]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[4])))
DONE;
})
@@ -3495,7 +3505,8 @@
[] (rtx *operands, rtx boardcast_scalar) {
emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
boardcast_scalar, operands[3], operands[4]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[4])))
DONE;
})
@@ -4006,7 +4017,8 @@
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
operands[2], operands[3], boardcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -4081,7 +4093,8 @@
emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
operands[2], operands[3], boardcast_scalar, operands[5],
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -4226,7 +4239,8 @@
emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
operands[2], operands[3], boardcast_scalar, operands[5],
operands[6], operands[7], operands[8], operands[9]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -4692,7 +4706,8 @@
emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
operands[2], operands[3], operands[4], boardcast_scalar,
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -4724,7 +4739,8 @@
emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
operands[2], operands[3], operands[4], boardcast_scalar,
operands[6], operands[7], operands[8]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[8])))
DONE;
})
@@ -5347,7 +5363,8 @@
emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
boardcast_scalar, operands[3], operands[4], operands[5],
operands[6], operands[7], operands[8], operands[9]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[9])))
DONE;
})
@@ -5644,7 +5661,8 @@
emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
boardcast_scalar, operands[3], operands[4], operands[5],
operands[6], operands[7], operands[8], operands[9]));
- }))
+ },
+ (riscv_vector::avl_type) INTVAL (operands[9])))
DONE;
})
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32
2023-10-28 2:05 [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32 Juzhe-Zhong
@ 2023-10-30 7:41 ` Robin Dapp
2023-10-30 7:49 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Robin Dapp @ 2023-10-30 7:41 UTC (permalink / raw)
To: Juzhe-Zhong, gcc-patches; +Cc: rdapp.gcc, kito.cheng, kito.cheng, jeffreyalaw
Thanks, LGTM.
Regards
Robin
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32
2023-10-30 7:41 ` Robin Dapp
@ 2023-10-30 7:49 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-10-30 7:49 UTC (permalink / raw)
To: Robin Dapp, Juzhe-Zhong, gcc-patches; +Cc: kito.cheng, kito.cheng, jeffreyalaw
Committed, thanks Robin.
Pan
-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com>
Sent: Monday, October 30, 2023 3:42 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; kito.cheng@sifive.com; kito.cheng@gmail.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32
Thanks, LGTM.
Regards
Robin
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-10-28 2:05 [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32 Juzhe-Zhong
2023-10-30 7:41 ` Robin Dapp
2023-10-30 7:49 ` Li, Pan2
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