* [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
@ 2023-11-10 8:14 pan2.li
2023-11-10 8:15 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2023-11-10 8:14 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
The internal-fn has support the FLOATN already. This patch
would like to re-enable the vector HFmode for the autovec for
below standard name mode iterators.
1. lrint<m><n>
2. llround<m><n>
For now the vector HFmodes are disabled to limit the impact,
and the underlying FP16 rint/round autovec will enable this
one by one.
gcc/ChangeLog:
* config/riscv/autovec.md: Disable vector HFmode for
rint, round, ceil and floor.
* config/riscv/vector-iterators.md: Add vector HFmode
for rint, round, ceil and floor mode iterator.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/autovec.md | 26 +++++++-----
gcc/config/riscv/vector-iterators.md | 59 +++++++++++++++++++++++++++-
2 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..a199caabf87 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2443,12 +2443,11 @@ (define_expand "roundeven<mode>2"
}
)
-;; Add mode_size equal check as we opened the modes for different sizes.
-;; The check will be removed soon after related codegen implemented
(define_expand "lrint<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2458,7 +2457,8 @@ (define_expand "lrint<mode><v_f2si_convert>2"
(define_expand "lrint<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2468,7 +2468,8 @@ (define_expand "lrint<mode><v_f2di_convert>2"
(define_expand "lround<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2478,7 +2479,8 @@ (define_expand "lround<mode><v_f2si_convert>2"
(define_expand "lround<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2488,7 +2490,8 @@ (define_expand "lround<mode><v_f2di_convert>2"
(define_expand "lceil<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2498,7 +2501,8 @@ (define_expand "lceil<mode><v_f2si_convert>2"
(define_expand "lceil<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2508,7 +2512,8 @@ (define_expand "lceil<mode><v_f2di_convert>2"
(define_expand "lfloor<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2518,7 +2523,8 @@ (define_expand "lfloor<mode><v_f2si_convert>2"
(define_expand "lfloor<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index e80eaedc4b3..f2d9f60b631 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3221,15 +3221,20 @@ (define_mode_attr vnnconvert [
;; V_F2SI_CONVERT: (HF, SF, DF) => SI
;; V_F2DI_CONVERT: (HF, SF, DF) => DI
;;
-;; HF requires additional support from internal function, aka
-;; gcc/internal-fn.def, remove HF shortly until the middle-end is ready.
(define_mode_attr V_F2SI_CONVERT [
+ (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI")
+ (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI")
+
(RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI")
(RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
(RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI")
(RVVM1DF "RVVMF2SI")
+ (V1HF "V1SI") (V2HF "V2SI") (V4HF "V4SI") (V8HF "V8SI") (V16HF "V16SI")
+ (V32HF "V32SI") (V64HF "V64SI") (V128HF "V128SI") (V256HF "V256SI")
+ (V512HF "V512SI") (V1024HF "V1024SI")
+
(V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI")
(V32SF "V32SI") (V64SF "V64SI") (V128SF "V128SI") (V256SF "V256SI")
(V512SF "V512SI") (V1024SF "V1024SI")
@@ -3240,12 +3245,19 @@ (define_mode_attr V_F2SI_CONVERT [
])
(define_mode_attr v_f2si_convert [
+ (RVVM4HF "rvvm8si") (RVVM2HF "rvvm4si") (RVVM1HF "rvvm2si")
+ (RVVMF2HF "rvvm1si") (RVVMF4HF "rvvmf2si")
+
(RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si")
(RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si")
(RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si")
(RVVM1DF "rvvmf2si")
+ (V1HF "v1si") (V2HF "v2si") (V4HF "v4si") (V8HF "v8si") (V16HF "v16si")
+ (V32HF "v32si") (V64HF "v64si") (V128HF "v128si") (V256HF "v256si")
+ (V512HF "v512si") (V1024HF "v1024si")
+
(V1SF "v1si") (V2SF "v2si") (V4SF "v4si") (V8SF "v8si") (V16SF "v16si")
(V32SF "v32si") (V64SF "v64si") (V128SF "v128si") (V256SF "v256si")
(V512SF "v512si") (V1024SF "v1024si")
@@ -3256,6 +3268,9 @@ (define_mode_attr v_f2si_convert [
])
(define_mode_iterator V_VLS_F_CONVERT_SI [
+ (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH")
+ (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
(RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
(RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
@@ -3265,6 +3280,18 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+ (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
+ (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
+ (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
+ (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
+ (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
+ (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+ (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
+
(V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
@@ -3290,12 +3317,19 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [
])
(define_mode_attr V_F2DI_CONVERT [
+ (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI")
+ (RVVMF4HF "RVVM1DI")
+
(RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI")
(RVVMF2SF "RVVM1DI")
(RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI")
(RVVM1DF "RVVM1DI")
+ (V1HF "V1DI") (V2HF "V2DI") (V4HF "V4DI") (V8HF "V8DI") (V16HF "V16DI")
+ (V32HF "V32DI") (V64HF "V64DI") (V128HF "V128DI") (V256HF "V256DI")
+ (V512HF "V512DI")
+
(V1SF "V1DI") (V2SF "V2DI") (V4SF "V4DI") (V8SF "V8DI") (V16SF "V16DI")
(V32SF "V32DI") (V64SF "V64DI") (V128SF "V128DI") (V256SF "V256DI")
(V512SF "V512DI")
@@ -3306,12 +3340,19 @@ (define_mode_attr V_F2DI_CONVERT [
])
(define_mode_attr v_f2di_convert [
+ (RVVM2HF "rvvm8di") (RVVM1HF "rvvm4di") (RVVMF2HF "rvvm2di")
+ (RVVMF4HF "rvvm1di")
+
(RVVM4SF "rvvm8di") (RVVM2SF "rvvm4di") (RVVM1SF "rvvm2di")
(RVVMF2SF "rvvm1di")
(RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di")
(RVVM1DF "rvvm1di")
+ (V1HF "v1di") (V2HF "v2di") (V4HF "v4di") (V8HF "v8di") (V16HF "v16di")
+ (V32HF "v32di") (V64HF "v64di") (V128HF "v128di") (V256HF "v256di")
+ (V512HF "v512di")
+
(V1SF "v1di") (V2SF "v2di") (V4SF "v4di") (V8SF "v8di") (V16SF "v16di")
(V32SF "v32di") (V64SF "v64di") (V128SF "v128di") (V256SF "v256di")
(V512SF "v512di")
@@ -3322,6 +3363,9 @@ (define_mode_attr v_f2di_convert [
])
(define_mode_iterator V_VLS_F_CONVERT_DI [
+ (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
+ (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
(RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
(RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
@@ -3329,6 +3373,17 @@ (define_mode_iterator V_VLS_F_CONVERT_DI [
(RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+ (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
+ (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
+ (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
+ (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
+ (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
+ (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+
(V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
2023-11-10 8:14 [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec pan2.li
@ 2023-11-10 8:15 ` juzhe.zhong
2023-11-10 8:24 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-11-10 8:15 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 12713 bytes --]
No test?
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-11-10 16:14
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li <pan2.li@intel.com>
The internal-fn has support the FLOATN already. This patch
would like to re-enable the vector HFmode for the autovec for
below standard name mode iterators.
1. lrint<m><n>
2. llround<m><n>
For now the vector HFmodes are disabled to limit the impact,
and the underlying FP16 rint/round autovec will enable this
one by one.
gcc/ChangeLog:
* config/riscv/autovec.md: Disable vector HFmode for
rint, round, ceil and floor.
* config/riscv/vector-iterators.md: Add vector HFmode
for rint, round, ceil and floor mode iterator.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/autovec.md | 26 +++++++-----
gcc/config/riscv/vector-iterators.md | 59 +++++++++++++++++++++++++++-
2 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..a199caabf87 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2443,12 +2443,11 @@ (define_expand "roundeven<mode>2"
}
)
-;; Add mode_size equal check as we opened the modes for different sizes.
-;; The check will be removed soon after related codegen implemented
(define_expand "lrint<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2458,7 +2457,8 @@ (define_expand "lrint<mode><v_f2si_convert>2"
(define_expand "lrint<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2468,7 +2468,8 @@ (define_expand "lrint<mode><v_f2di_convert>2"
(define_expand "lround<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2478,7 +2479,8 @@ (define_expand "lround<mode><v_f2si_convert>2"
(define_expand "lround<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2488,7 +2490,8 @@ (define_expand "lround<mode><v_f2di_convert>2"
(define_expand "lceil<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2498,7 +2501,8 @@ (define_expand "lceil<mode><v_f2si_convert>2"
(define_expand "lceil<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2508,7 +2512,8 @@ (define_expand "lceil<mode><v_f2di_convert>2"
(define_expand "lfloor<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2518,7 +2523,8 @@ (define_expand "lfloor<mode><v_f2si_convert>2"
(define_expand "lfloor<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index e80eaedc4b3..f2d9f60b631 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3221,15 +3221,20 @@ (define_mode_attr vnnconvert [
;; V_F2SI_CONVERT: (HF, SF, DF) => SI
;; V_F2DI_CONVERT: (HF, SF, DF) => DI
;;
-;; HF requires additional support from internal function, aka
-;; gcc/internal-fn.def, remove HF shortly until the middle-end is ready.
(define_mode_attr V_F2SI_CONVERT [
+ (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI")
+ (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI")
+
(RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI")
(RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
(RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI")
(RVVM1DF "RVVMF2SI")
+ (V1HF "V1SI") (V2HF "V2SI") (V4HF "V4SI") (V8HF "V8SI") (V16HF "V16SI")
+ (V32HF "V32SI") (V64HF "V64SI") (V128HF "V128SI") (V256HF "V256SI")
+ (V512HF "V512SI") (V1024HF "V1024SI")
+
(V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI")
(V32SF "V32SI") (V64SF "V64SI") (V128SF "V128SI") (V256SF "V256SI")
(V512SF "V512SI") (V1024SF "V1024SI")
@@ -3240,12 +3245,19 @@ (define_mode_attr V_F2SI_CONVERT [
])
(define_mode_attr v_f2si_convert [
+ (RVVM4HF "rvvm8si") (RVVM2HF "rvvm4si") (RVVM1HF "rvvm2si")
+ (RVVMF2HF "rvvm1si") (RVVMF4HF "rvvmf2si")
+
(RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si")
(RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si")
(RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si")
(RVVM1DF "rvvmf2si")
+ (V1HF "v1si") (V2HF "v2si") (V4HF "v4si") (V8HF "v8si") (V16HF "v16si")
+ (V32HF "v32si") (V64HF "v64si") (V128HF "v128si") (V256HF "v256si")
+ (V512HF "v512si") (V1024HF "v1024si")
+
(V1SF "v1si") (V2SF "v2si") (V4SF "v4si") (V8SF "v8si") (V16SF "v16si")
(V32SF "v32si") (V64SF "v64si") (V128SF "v128si") (V256SF "v256si")
(V512SF "v512si") (V1024SF "v1024si")
@@ -3256,6 +3268,9 @@ (define_mode_attr v_f2si_convert [
])
(define_mode_iterator V_VLS_F_CONVERT_SI [
+ (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH")
+ (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
(RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
(RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
@@ -3265,6 +3280,18 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+ (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
+ (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
+ (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
+ (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
+ (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
+ (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+ (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
+
(V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
@@ -3290,12 +3317,19 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [
])
(define_mode_attr V_F2DI_CONVERT [
+ (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI")
+ (RVVMF4HF "RVVM1DI")
+
(RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI")
(RVVMF2SF "RVVM1DI")
(RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI")
(RVVM1DF "RVVM1DI")
+ (V1HF "V1DI") (V2HF "V2DI") (V4HF "V4DI") (V8HF "V8DI") (V16HF "V16DI")
+ (V32HF "V32DI") (V64HF "V64DI") (V128HF "V128DI") (V256HF "V256DI")
+ (V512HF "V512DI")
+
(V1SF "V1DI") (V2SF "V2DI") (V4SF "V4DI") (V8SF "V8DI") (V16SF "V16DI")
(V32SF "V32DI") (V64SF "V64DI") (V128SF "V128DI") (V256SF "V256DI")
(V512SF "V512DI")
@@ -3306,12 +3340,19 @@ (define_mode_attr V_F2DI_CONVERT [
])
(define_mode_attr v_f2di_convert [
+ (RVVM2HF "rvvm8di") (RVVM1HF "rvvm4di") (RVVMF2HF "rvvm2di")
+ (RVVMF4HF "rvvm1di")
+
(RVVM4SF "rvvm8di") (RVVM2SF "rvvm4di") (RVVM1SF "rvvm2di")
(RVVMF2SF "rvvm1di")
(RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di")
(RVVM1DF "rvvm1di")
+ (V1HF "v1di") (V2HF "v2di") (V4HF "v4di") (V8HF "v8di") (V16HF "v16di")
+ (V32HF "v32di") (V64HF "v64di") (V128HF "v128di") (V256HF "v256di")
+ (V512HF "v512di")
+
(V1SF "v1di") (V2SF "v2di") (V4SF "v4di") (V8SF "v8di") (V16SF "v16di")
(V32SF "v32di") (V64SF "v64di") (V128SF "v128di") (V256SF "v256di")
(V512SF "v512di")
@@ -3322,6 +3363,9 @@ (define_mode_attr v_f2di_convert [
])
(define_mode_iterator V_VLS_F_CONVERT_DI [
+ (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
+ (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
(RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
(RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
@@ -3329,6 +3373,17 @@ (define_mode_iterator V_VLS_F_CONVERT_DI [
(RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+ (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
+ (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
+ (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
+ (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
+ (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
+ (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+
(V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
2023-11-10 8:15 ` juzhe.zhong
@ 2023-11-10 8:24 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-11-10 8:24 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 13545 bytes --]
This patch only add new modes to iterator, I failed to find a way to test it.
Maybe I can add underlying lrint autovec implment together, which is more straightforward
to add test cases here.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, November 10, 2023 4:16 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
No test?
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-11-10 16:14
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
The internal-fn has support the FLOATN already. This patch
would like to re-enable the vector HFmode for the autovec for
below standard name mode iterators.
1. lrint<m><n>
2. llround<m><n>
For now the vector HFmodes are disabled to limit the impact,
and the underlying FP16 rint/round autovec will enable this
one by one.
gcc/ChangeLog:
* config/riscv/autovec.md: Disable vector HFmode for
rint, round, ceil and floor.
* config/riscv/vector-iterators.md: Add vector HFmode
for rint, round, ceil and floor mode iterator.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/config/riscv/autovec.md | 26 +++++++-----
gcc/config/riscv/vector-iterators.md | 59 +++++++++++++++++++++++++++-
2 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..a199caabf87 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2443,12 +2443,11 @@ (define_expand "roundeven<mode>2"
}
)
-;; Add mode_size equal check as we opened the modes for different sizes.
-;; The check will be removed soon after related codegen implemented
(define_expand "lrint<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2458,7 +2457,8 @@ (define_expand "lrint<mode><v_f2si_convert>2"
(define_expand "lrint<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lrint (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2468,7 +2468,8 @@ (define_expand "lrint<mode><v_f2di_convert>2"
(define_expand "lround<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2478,7 +2479,8 @@ (define_expand "lround<mode><v_f2si_convert>2"
(define_expand "lround<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lround (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2488,7 +2490,8 @@ (define_expand "lround<mode><v_f2di_convert>2"
(define_expand "lceil<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2498,7 +2501,8 @@ (define_expand "lceil<mode><v_f2si_convert>2"
(define_expand "lceil<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lceil (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
@@ -2508,7 +2512,8 @@ (define_expand "lceil<mode><v_f2di_convert>2"
(define_expand "lfloor<mode><v_f2si_convert>2"
[(match_operand:<V_F2SI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], <MODE>mode, <V_F2SI_CONVERT>mode);
DONE;
@@ -2518,7 +2523,8 @@ (define_expand "lfloor<mode><v_f2si_convert>2"
(define_expand "lfloor<mode><v_f2di_convert>2"
[(match_operand:<V_F2DI_CONVERT> 0 "register_operand")
(match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")]
- "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math"
+ "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math
+ && GET_MODE_INNER (<MODE>mode) != HFmode"
{
riscv_vector::expand_vec_lfloor (operands[0], operands[1], <MODE>mode, <V_F2DI_CONVERT>mode);
DONE;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index e80eaedc4b3..f2d9f60b631 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3221,15 +3221,20 @@ (define_mode_attr vnnconvert [
;; V_F2SI_CONVERT: (HF, SF, DF) => SI
;; V_F2DI_CONVERT: (HF, SF, DF) => DI
;;
-;; HF requires additional support from internal function, aka
-;; gcc/internal-fn.def, remove HF shortly until the middle-end is ready.
(define_mode_attr V_F2SI_CONVERT [
+ (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI")
+ (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI")
+
(RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI")
(RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
(RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI")
(RVVM1DF "RVVMF2SI")
+ (V1HF "V1SI") (V2HF "V2SI") (V4HF "V4SI") (V8HF "V8SI") (V16HF "V16SI")
+ (V32HF "V32SI") (V64HF "V64SI") (V128HF "V128SI") (V256HF "V256SI")
+ (V512HF "V512SI") (V1024HF "V1024SI")
+
(V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI")
(V32SF "V32SI") (V64SF "V64SI") (V128SF "V128SI") (V256SF "V256SI")
(V512SF "V512SI") (V1024SF "V1024SI")
@@ -3240,12 +3245,19 @@ (define_mode_attr V_F2SI_CONVERT [
])
(define_mode_attr v_f2si_convert [
+ (RVVM4HF "rvvm8si") (RVVM2HF "rvvm4si") (RVVM1HF "rvvm2si")
+ (RVVMF2HF "rvvm1si") (RVVMF4HF "rvvmf2si")
+
(RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si")
(RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si")
(RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si")
(RVVM1DF "rvvmf2si")
+ (V1HF "v1si") (V2HF "v2si") (V4HF "v4si") (V8HF "v8si") (V16HF "v16si")
+ (V32HF "v32si") (V64HF "v64si") (V128HF "v128si") (V256HF "v256si")
+ (V512HF "v512si") (V1024HF "v1024si")
+
(V1SF "v1si") (V2SF "v2si") (V4SF "v4si") (V8SF "v8si") (V16SF "v16si")
(V32SF "v32si") (V64SF "v64si") (V128SF "v128si") (V256SF "v256si")
(V512SF "v512si") (V1024SF "v1024si")
@@ -3256,6 +3268,9 @@ (define_mode_attr v_f2si_convert [
])
(define_mode_iterator V_VLS_F_CONVERT_SI [
+ (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH")
+ (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
(RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
(RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
@@ -3265,6 +3280,18 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+ (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
+ (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
+ (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
+ (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
+ (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
+ (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+ (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
+
(V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
@@ -3290,12 +3317,19 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [
])
(define_mode_attr V_F2DI_CONVERT [
+ (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI")
+ (RVVMF4HF "RVVM1DI")
+
(RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI")
(RVVMF2SF "RVVM1DI")
(RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI")
(RVVM1DF "RVVM1DI")
+ (V1HF "V1DI") (V2HF "V2DI") (V4HF "V4DI") (V8HF "V8DI") (V16HF "V16DI")
+ (V32HF "V32DI") (V64HF "V64DI") (V128HF "V128DI") (V256HF "V256DI")
+ (V512HF "V512DI")
+
(V1SF "V1DI") (V2SF "V2DI") (V4SF "V4DI") (V8SF "V8DI") (V16SF "V16DI")
(V32SF "V32DI") (V64SF "V64DI") (V128SF "V128DI") (V256SF "V256DI")
(V512SF "V512DI")
@@ -3306,12 +3340,19 @@ (define_mode_attr V_F2DI_CONVERT [
])
(define_mode_attr v_f2di_convert [
+ (RVVM2HF "rvvm8di") (RVVM1HF "rvvm4di") (RVVMF2HF "rvvm2di")
+ (RVVMF4HF "rvvm1di")
+
(RVVM4SF "rvvm8di") (RVVM2SF "rvvm4di") (RVVM1SF "rvvm2di")
(RVVMF2SF "rvvm1di")
(RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di")
(RVVM1DF "rvvm1di")
+ (V1HF "v1di") (V2HF "v2di") (V4HF "v4di") (V8HF "v8di") (V16HF "v16di")
+ (V32HF "v32di") (V64HF "v64di") (V128HF "v128di") (V256HF "v256di")
+ (V512HF "v512di")
+
(V1SF "v1di") (V2SF "v2di") (V4SF "v4di") (V8SF "v8di") (V16SF "v16di")
(V32SF "v32di") (V64SF "v64di") (V128SF "v128di") (V256SF "v256di")
(V512SF "v512di")
@@ -3322,6 +3363,9 @@ (define_mode_attr v_f2di_convert [
])
(define_mode_iterator V_VLS_F_CONVERT_DI [
+ (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
+ (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
(RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
(RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
(RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
@@ -3329,6 +3373,17 @@ (define_mode_iterator V_VLS_F_CONVERT_DI [
(RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
+ (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
+ (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
+ (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
+ (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
+ (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
+ (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
+ (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
+ (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
+ (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
+ (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
+
(V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
(V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-11-10 8:25 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2023-11-10 8:14 [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec pan2.li
2023-11-10 8:15 ` juzhe.zhong
2023-11-10 8:24 ` Li, Pan2
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