From: "Li, Pan2" <pan2.li@intel.com>
To: Jeff Law <jeffreyalaw@gmail.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
"kito.cheng@gmail.com" <kito.cheng@gmail.com>,
"richard.guenther@gmail.com" <richard.guenther@gmail.com>,
"Wang, Yanzhang" <yanzhang.wang@intel.com>,
"rdapp.gcc@gmail.com" <rdapp.gcc@gmail.com>,
"Liu, Hongtao" <hongtao.liu@intel.com>
Subject: RE: [PATCH v2] DSE: Bugfix ICE after allow vector type in get_stored_val
Date: Thu, 29 Feb 2024 01:38:21 +0000 [thread overview]
Message-ID: <MW5PR11MB59085A54CC6DFF9B8FBC27C2A95F2@MW5PR11MB5908.namprd11.prod.outlook.com> (raw)
In-Reply-To: <793c14cb-2a08-41a4-ac55-4c39295f42d3@gmail.com>
> So it's going to check if V2SF can be tied to DI and V4QI with SI. I
> suspect those are going to fail for RISC-V as those aren't tieable.
Yes, you are right. Different REG_CLASS are not allowed to be tieable in RISC-V.
static bool
riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
/* We don't allow different REG_CLASS modes tieable since it
will cause ICE in register allocation (RA).
E.g. V2SI and DI are not tieable. */
if (riscv_v_ext_mode_p (mode1) != riscv_v_ext_mode_p (mode2))
return false;
return (mode1 == mode2
|| !(GET_MODE_CLASS (mode1) == MODE_FLOAT
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));
}
Pan
-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com>
Sent: Thursday, February 29, 2024 1:33 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; richard.guenther@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; Liu, Hongtao <hongtao.liu@intel.com>
Subject: Re: [PATCH v2] DSE: Bugfix ICE after allow vector type in get_stored_val
On 2/27/24 21:51, Li, Pan2 wrote:
>> if (!targetm.modes_tieable_p (src_int_mode, src_mode))
>> return NULL_RTX;
>> if (!targetm.modes_tieable_p (int_mode, mode))
>> return NULL_RTX;
>
> Yes, will return NULL_RTX for in the first if, given src_int_mode is E_DImode while src_mode is
> E_V2SFmode and mode is E_V4QImode. The extract_low_bits convert the modes E_V2SFmode/E_V4QImode
> to E_DImode/E_SImode in advance before tieable checking, validate_subreg and gen_lowpart.
>
> Not sure if my understanding is correct but looks extract_low_bits cannot take care of vector modes
> up to a point because vector modes are always untieable to its' int mode, and then return NULL_RTX.
Well, the code tries to turn the vector mode into a suitable integer
mode via int_mode_for_mode. That takes a mode, including vector modes
and tries to find an integer mode of the exact same size.
So it's going to check if V2SF can be tied to DI and V4QI with SI. I
suspect those are going to fail for RISC-V as those aren't tieable.
Jeff
next prev parent reply other threads:[~2024-02-29 1:38 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-26 3:25 [PATCH v1] RTL: Bugfix ICE after allow vector type in DSE pan2.li
2024-02-26 3:41 ` Hongtao Liu
2024-02-26 3:42 ` Li, Pan2
2024-02-26 5:13 ` Hongtao Liu
2024-02-26 7:38 ` Richard Biener
2024-02-26 7:41 ` Li, Pan2
2024-02-26 14:22 ` [PATCH v2] DSE: Bugfix ICE after allow vector type in get_stored_val pan2.li
2024-02-27 9:47 ` Richard Biener
2024-02-27 15:02 ` Jeff Law
2024-02-28 1:40 ` Li, Pan2
2024-02-28 4:51 ` Li, Pan2
2024-02-28 17:33 ` Jeff Law
2024-02-29 1:38 ` Li, Pan2 [this message]
2024-02-29 13:28 ` Robin Dapp
2024-03-02 1:04 ` Li, Pan2
2024-03-03 22:46 ` Jeff Law
2024-03-05 6:22 ` Li, Pan2
2024-03-12 2:08 ` Li, Pan2
2024-03-22 1:15 ` Li, Pan2
2024-03-22 18:53 ` Jeff Law
2024-03-23 5:45 ` Li, Pan2
2024-04-06 12:02 ` Li, Pan2
2024-04-18 1:46 ` Li, Pan2
2024-04-28 12:10 ` Li, Pan2
2024-04-29 15:20 ` Jeff Law
2024-04-30 1:02 ` Li, Pan2
2024-04-30 7:17 ` [PATCH v3] DSE: Fix " pan2.li
2024-04-30 11:35 ` Li, Pan2
2024-05-03 1:57 ` Li, Pan2
2024-05-03 1:51 ` [PATCH v4] " pan2.li
2024-05-16 4:06 ` Li, Pan2
2024-05-19 16:23 ` Jeff Law
2024-05-20 1:08 ` Li, Pan2
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