RE: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

["Li, Pan2" <pan2.li@intel.com>]

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Thanks Juzhe, Just passed the RV64 riscv/rvv.exp but meet some failures in RV32 the same as upstream. However, this patch may not introduce new failures but I am not quite sure if there is risk here.

lowlist `find build-gcc-newlib-stage2/gcc/testsuite/ -name *.sum |paste -sd "," -`
                === gcc: Unexpected fails for rv32imafdcv ilp32f medlow ===
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution test
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax execution test
FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-run.c -O3 -ftree-vectorize (test for excess errors)
                === g++: Unexpected fails for rv32imafdcv ilp32f medlow ===
FAIL: g++.target/riscv/rvv/base/bug-14.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-9.C (test for excess errors)

               ========= Summary of gcc testsuite =========
                            | # of unexpected case / # of unique unexpected case
                            |          gcc |          g++ |     gfortran |
rv32imafdcv/ ilp32f/ medlow |    7 /     4 |    2 /     2 |      - |

For RV32, mostly I take below commands for testing.

cd riscv-gnu-toolchain
cd gcc && git checkout master && git pull -p && cd -
cd spike && git checkout master && git pull -p && cd -
cd pk && git checkout master && git pull -p && cd -

./configure --prefix=`pwd`/__RISC-V_INSTALL_/ --with-arch=rv32imafdcv --with-abi=ilp32f --with-isa-spec=20191213 --with-sim=spike
make -j $(nproc) build-sim SIM=spike
make report -j $(nproc) RUNTESTFLAGS="rvv.exp"

Pan

From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, June 14, 2023 10:31 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

LGTM.

________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-14 10:15
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch is considered as the follow up of the below PATCH.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621347.html

We aligned the predictor style for the define_insn_and_split suggested
by Kito. To avoid potential issues before we hit.

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Align the predictor sytle.
* config/riscv/autovec.md: Ditto.
---
gcc/config/riscv/autovec-opt.md | 20 ++++++++++----------
gcc/config/riscv/autovec.md     | 24 ++++++++++++------------
2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index aef28e445e1..fb1b07205aa 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -37,9 +37,9 @@ (define_insn_and_split "@pred_single_widen_mul<any_extend:su><mode>"
      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr"))
    (match_operand:VWEXTI 3 "register_operand"             "   vr,   vr"))
  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
     insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode);
@@ -132,9 +132,9 @@ (define_insn_and_split "*<optab>not<mode>"
(bitmanip_bitwise:VB
  (not:VB (match_operand:VB 2 "register_operand" " vr"))
  (match_operand:VB 1 "register_operand"         " vr")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
     insn_code icode = code_for_pred_not (<CODE>, <MODE>mode);
@@ -159,9 +159,9 @@ (define_insn_and_split "*n<optab><mode>"
  (any_bitwise:VB
    (match_operand:VB 1 "register_operand" " vr")
    (match_operand:VB 2 "register_operand" " vr"))))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
     insn_code icode = code_for_pred_n (<CODE>, <MODE>mode);
@@ -346,9 +346,9 @@ (define_insn_and_split "*v<any_shiftrt:optab><any_extend:optab>trunc<mode>"
         (match_operand:VWEXTI 1 "register_operand"                 " vr,vr")
(any_extend:VWEXTI
           (match_operand:<V_DOUBLE_TRUNC> 2 "vector_shift_operand" " vr,vk")))))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
{
   insn_code icode = code_for_pred_narrow (<any_shiftrt:CODE>, <MODE>mode);
@@ -364,9 +364,9 @@ (define_insn_and_split "*<any_shiftrt:optab>trunc<mode>"
       (any_shiftrt:VWEXTI
         (match_operand:VWEXTI 1 "register_operand"           " vr")
(match_operand:<VEL> 2 "csr_operand"                 " rK"))))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
{
   operands[2] = gen_lowpart (Pmode, operands[2]);
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index eadc2c5b595..c23a625afe1 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -155,9 +155,9 @@ (define_insn_and_split "<optab><mode>3"
     (any_shift:VI
      (match_operand:VI 1 "register_operand"    " vr")
      (match_operand:<VEL> 2 "csr_operand"      " rK")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
{
   operands[2] = gen_lowpart (Pmode, operands[2]);
@@ -180,9 +180,9 @@ (define_insn_and_split "v<optab><mode>3"
     (any_shift:VI
      (match_operand:VI 1 "register_operand"     " vr,vr")
      (match_operand:VI 2 "vector_shift_operand" " vr,vk")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
{
   riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
@@ -205,9 +205,9 @@ (define_insn_and_split "<optab><mode>3"
   [(set (match_operand:VB 0 "register_operand"                 "=vr")
(any_bitwise:VB (match_operand:VB 1 "register_operand" " vr")
(match_operand:VB 2 "register_operand" " vr")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
     insn_code icode = code_for_pred (<CODE>, <MODE>mode);
@@ -227,9 +227,9 @@ (define_insn_and_split "<optab><mode>3"
(define_insn_and_split "one_cmpl<mode>2"
   [(set (match_operand:VB 0 "register_operand"         "=vr")
(not:VB (match_operand:VB 1 "register_operand" " vr")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
     insn_code icode = code_for_pred_not (<MODE>mode);
@@ -366,9 +366,9 @@ (define_insn_and_split "<optab><v_double_trunc><mode>2"
   [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
     (any_extend:VWEXTI
      (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand" "vr")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
{
   insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode);
@@ -409,9 +409,9 @@ (define_insn_and_split "trunc<mode><v_double_trunc>2"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr")
     (truncate:<V_DOUBLE_TRUNC>
      (match_operand:VWEXTI 1 "register_operand"              " vr")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
{
   insn_code icode = code_for_pred_trunc (<MODE>mode);
--
2.34.1