* [PATCH] RISC-V: Fix misspelled term builtin in error message
@ 2024-03-30 12:07 pan2.li
2024-03-31 1:04 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2024-03-30 12:07 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, yanzhang.wang, Pan Li
From: Pan Li <pan2.li@intel.com>
This patch would like to fix below misspelled term in error message.
../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error:
misspelled term 'builtin function' in format; use 'built-in function' instead [-Werror=format-diag]
4592 | "builtin function %qE requires the V ISA extension", exp);
The below tests are passed for this patch.
* The riscv regression test on rvv.exp and riscv.exp.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
the term built-in over builtin.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
Adjust test dg-error.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
.../riscv/rvv/base/target_attribute_v_with_intrinsic-7.c | 2 +-
.../riscv/rvv/base/target_attribute_v_with_intrinsic-8.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index e07373d8b57..db9246eed2d 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
if (!TARGET_VECTOR)
error_at (EXPR_LOCATION (exp),
- "builtin function %qE requires the V ISA extension", exp);
+ "built-in function %qE requires the V ISA extension", exp);
return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
index 520b2e59fae..a4cd67f4f95 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
@@ -5,5 +5,5 @@
size_t test_1 (size_t vl)
{
- return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
+ return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
index 9032d9d0b43..06ed9a9eddc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
@@ -19,5 +19,5 @@ test_2 ()
size_t
test_3 (size_t vl)
{
- return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
+ return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
}
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Fix misspelled term builtin in error message
2024-03-30 12:07 [PATCH] RISC-V: Fix misspelled term builtin in error message pan2.li
@ 2024-03-31 1:04 ` Kito Cheng
2024-03-31 10:38 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2024-03-31 1:04 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, yanzhang.wang
lgtm
On Sat, Mar 30, 2024 at 8:07 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to fix below misspelled term in error message.
>
> ../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error:
> misspelled term 'builtin function' in format; use 'built-in function' instead [-Werror=format-diag]
> 4592 | "builtin function %qE requires the V ISA extension", exp);
>
> The below tests are passed for this patch.
> * The riscv regression test on rvv.exp and riscv.exp.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
> the term built-in over builtin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
> Adjust test dg-error.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
> Ditto.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
> .../riscv/rvv/base/target_attribute_v_with_intrinsic-7.c | 2 +-
> .../riscv/rvv/base/target_attribute_v_with_intrinsic-8.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index e07373d8b57..db9246eed2d 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>
> if (!TARGET_VECTOR)
> error_at (EXPR_LOCATION (exp),
> - "builtin function %qE requires the V ISA extension", exp);
> + "built-in function %qE requires the V ISA extension", exp);
>
> return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> index 520b2e59fae..a4cd67f4f95 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> @@ -5,5 +5,5 @@
>
> size_t test_1 (size_t vl)
> {
> - return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> + return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> index 9032d9d0b43..06ed9a9eddc 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> @@ -19,5 +19,5 @@ test_2 ()
> size_t
> test_3 (size_t vl)
> {
> - return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> + return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] RISC-V: Fix misspelled term builtin in error message
2024-03-31 1:04 ` Kito Cheng
@ 2024-03-31 10:38 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2024-03-31 10:38 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, Wang, Yanzhang
Committed, thanks Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Sunday, March 31, 2024 9:05 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: Fix misspelled term builtin in error message
lgtm
On Sat, Mar 30, 2024 at 8:07 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to fix below misspelled term in error message.
>
> ../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error:
> misspelled term 'builtin function' in format; use 'built-in function' instead [-Werror=format-diag]
> 4592 | "builtin function %qE requires the V ISA extension", exp);
>
> The below tests are passed for this patch.
> * The riscv regression test on rvv.exp and riscv.exp.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
> the term built-in over builtin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
> Adjust test dg-error.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
> Ditto.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
> .../riscv/rvv/base/target_attribute_v_with_intrinsic-7.c | 2 +-
> .../riscv/rvv/base/target_attribute_v_with_intrinsic-8.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index e07373d8b57..db9246eed2d 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>
> if (!TARGET_VECTOR)
> error_at (EXPR_LOCATION (exp),
> - "builtin function %qE requires the V ISA extension", exp);
> + "built-in function %qE requires the V ISA extension", exp);
>
> return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> index 520b2e59fae..a4cd67f4f95 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> @@ -5,5 +5,5 @@
>
> size_t test_1 (size_t vl)
> {
> - return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> + return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> index 9032d9d0b43..06ed9a9eddc 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> @@ -19,5 +19,5 @@ test_2 ()
> size_t
> test_3 (size_t vl)
> {
> - return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> + return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-03-30 12:07 [PATCH] RISC-V: Fix misspelled term builtin in error message pan2.li
2024-03-31 1:04 ` Kito Cheng
2024-03-31 10:38 ` Li, Pan2
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