* [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics
@ 2023-05-17 1:51 juzhe.zhong
2023-05-17 3:01 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-05-17 1:51 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc,
Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Hi, since fixed-point with modeling rounding mode intrinsics are coming:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
I am adding vxrm rounding mode enum to user first before the API intrinsic.
This patch is simple && obvious.
Ok for trunk ?
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (register_vxrm): New function.
(DEF_RVV_VXRM_ENUM): New macro.
(handle_pragma_vector): Add vxrm enum register.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_VXRM_ENUM): New macro.
(RNU): Ditto.
(RNE): Ditto.
(RDN): Ditto.
(ROD): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vxrm-1.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.cc | 16 ++++++++++
gcc/config/riscv/riscv-vector-builtins.def | 11 +++++++
.../gcc.target/riscv/rvv/base/vxrm-1.c | 29 +++++++++++++++++++
3 files changed, 56 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index b7458aaace6..bcabf1ea1a6 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3740,6 +3740,19 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type,
gcc_unreachable ();
}
+/* Register the vxrm enum. */
+static void
+register_vxrm ()
+{
+ auto_vec<string_int_pair, 4> values;
+#define DEF_RVV_VXRM_ENUM(NAME, VALUE) \
+ values.quick_push (string_int_pair ("VXRM_" #NAME, VALUE));
+#include "riscv-vector-builtins.def"
+#undef DEF_RVV_VXRM_ENUM
+
+ lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values);
+}
+
/* Implement #pragma riscv intrinsic vector. */
void
handle_pragma_vector ()
@@ -3755,6 +3768,9 @@ handle_pragma_vector ()
for (unsigned int type_i = 0; type_i < NUM_VECTOR_TYPES; ++type_i)
register_vector_type ((enum vector_type_index) type_i);
+ /* Define the enums. */
+ register_vxrm ();
+
/* Define the functions. */
function_table = new hash_table<registered_function_hasher> (1023);
function_builder builder;
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 0a387fd1617..2a1a9dbc903 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -83,6 +83,11 @@ along with GCC; see the file COPYING3. If not see
X64_VLMUL_EXT, TUPLE_SUBPART)
#endif
+/* Define RVV_VXRM rounding mode enum for fixed-point intrinsics. */
+#ifndef DEF_RVV_VXRM_ENUM
+#define DEF_RVV_VXRM_ENUM(NAME, VALUE)
+#endif
+
/* SEW/LMUL = 64:
Only enable when TARGET_MIN_VLEN > 32.
Machine mode = VNx1BImode when TARGET_MIN_VLEN < 128.
@@ -643,6 +648,11 @@ DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type (type_idx))
DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node))
DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx))
+DEF_RVV_VXRM_ENUM (RNU, VXRM_RNU)
+DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE)
+DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN)
+DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
+
#include "riscv-vector-type-indexer.gen.def"
#undef DEF_RVV_PRED_TYPE
@@ -651,3 +661,4 @@ DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx))
#undef DEF_RVV_TUPLE_TYPE
#undef DEF_RVV_BASE_TYPE
#undef DEF_RVV_TYPE_INDEX
+#undef DEF_RVV_VXRM_ENUM
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
new file mode 100644
index 00000000000..0d364787ad0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t f0 ()
+{
+ return VXRM_RNU;
+}
+
+size_t f1 ()
+{
+ return VXRM_RNE;
+}
+
+size_t f2 ()
+{
+ return VXRM_RDN;
+}
+
+size_t f3 ()
+{
+ return VXRM_ROD;
+}
+
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics
2023-05-17 1:51 [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics juzhe.zhong
@ 2023-05-17 3:01 ` Kito Cheng
2023-05-17 14:56 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2023-05-17 3:01 UTC (permalink / raw)
To: juzhe.zhong
Cc: gcc-patches, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc
I would like to defer this until the PR has updated.
On Wed, May 17, 2023 at 9:52 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Hi, since fixed-point with modeling rounding mode intrinsics are coming:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
>
> I am adding vxrm rounding mode enum to user first before the API intrinsic.
>
> This patch is simple && obvious.
>
> Ok for trunk ?
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (register_vxrm): New function.
> (DEF_RVV_VXRM_ENUM): New macro.
> (handle_pragma_vector): Add vxrm enum register.
> * config/riscv/riscv-vector-builtins.def (DEF_RVV_VXRM_ENUM): New macro.
> (RNU): Ditto.
> (RNE): Ditto.
> (RDN): Ditto.
> (ROD): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vxrm-1.c: New test.
>
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 16 ++++++++++
> gcc/config/riscv/riscv-vector-builtins.def | 11 +++++++
> .../gcc.target/riscv/rvv/base/vxrm-1.c | 29 +++++++++++++++++++
> 3 files changed, 56 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index b7458aaace6..bcabf1ea1a6 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3740,6 +3740,19 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type,
> gcc_unreachable ();
> }
>
> +/* Register the vxrm enum. */
> +static void
> +register_vxrm ()
> +{
> + auto_vec<string_int_pair, 4> values;
> +#define DEF_RVV_VXRM_ENUM(NAME, VALUE) \
> + values.quick_push (string_int_pair ("VXRM_" #NAME, VALUE));
> +#include "riscv-vector-builtins.def"
> +#undef DEF_RVV_VXRM_ENUM
> +
> + lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values);
> +}
> +
> /* Implement #pragma riscv intrinsic vector. */
> void
> handle_pragma_vector ()
> @@ -3755,6 +3768,9 @@ handle_pragma_vector ()
> for (unsigned int type_i = 0; type_i < NUM_VECTOR_TYPES; ++type_i)
> register_vector_type ((enum vector_type_index) type_i);
>
> + /* Define the enums. */
> + register_vxrm ();
> +
> /* Define the functions. */
> function_table = new hash_table<registered_function_hasher> (1023);
> function_builder builder;
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
> index 0a387fd1617..2a1a9dbc903 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -83,6 +83,11 @@ along with GCC; see the file COPYING3. If not see
> X64_VLMUL_EXT, TUPLE_SUBPART)
> #endif
>
> +/* Define RVV_VXRM rounding mode enum for fixed-point intrinsics. */
> +#ifndef DEF_RVV_VXRM_ENUM
> +#define DEF_RVV_VXRM_ENUM(NAME, VALUE)
> +#endif
> +
> /* SEW/LMUL = 64:
> Only enable when TARGET_MIN_VLEN > 32.
> Machine mode = VNx1BImode when TARGET_MIN_VLEN < 128.
> @@ -643,6 +648,11 @@ DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node))
> DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx))
>
> +DEF_RVV_VXRM_ENUM (RNU, VXRM_RNU)
> +DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE)
> +DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN)
> +DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
> +
> #include "riscv-vector-type-indexer.gen.def"
>
> #undef DEF_RVV_PRED_TYPE
> @@ -651,3 +661,4 @@ DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx))
> #undef DEF_RVV_TUPLE_TYPE
> #undef DEF_RVV_BASE_TYPE
> #undef DEF_RVV_TYPE_INDEX
> +#undef DEF_RVV_VXRM_ENUM
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
> new file mode 100644
> index 00000000000..0d364787ad0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +size_t f0 ()
> +{
> + return VXRM_RNU;
> +}
> +
> +size_t f1 ()
> +{
> + return VXRM_RNE;
> +}
> +
> +size_t f2 ()
> +{
> + return VXRM_RDN;
> +}
> +
> +size_t f3 ()
> +{
> + return VXRM_ROD;
> +}
> +
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics
2023-05-17 3:01 ` Kito Cheng
@ 2023-05-17 14:56 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-05-17 14:56 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong
Cc: gcc-patches, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc
Committed as the below doc PR updated, thanks kito.
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches
Sent: Wednesday, May 17, 2023 11:01 AM
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.cheng@gmail.com; palmer@dabbelt.com; palmer@rivosinc.com; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics
I would like to defer this until the PR has updated.
On Wed, May 17, 2023 at 9:52 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Hi, since fixed-point with modeling rounding mode intrinsics are coming:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
>
> I am adding vxrm rounding mode enum to user first before the API intrinsic.
>
> This patch is simple && obvious.
>
> Ok for trunk ?
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (register_vxrm): New function.
> (DEF_RVV_VXRM_ENUM): New macro.
> (handle_pragma_vector): Add vxrm enum register.
> * config/riscv/riscv-vector-builtins.def (DEF_RVV_VXRM_ENUM): New macro.
> (RNU): Ditto.
> (RNE): Ditto.
> (RDN): Ditto.
> (ROD): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vxrm-1.c: New test.
>
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 16 ++++++++++
> gcc/config/riscv/riscv-vector-builtins.def | 11 +++++++
> .../gcc.target/riscv/rvv/base/vxrm-1.c | 29 +++++++++++++++++++
> 3 files changed, 56 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index b7458aaace6..bcabf1ea1a6 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3740,6 +3740,19 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type,
> gcc_unreachable ();
> }
>
> +/* Register the vxrm enum. */
> +static void
> +register_vxrm ()
> +{
> + auto_vec<string_int_pair, 4> values;
> +#define DEF_RVV_VXRM_ENUM(NAME, VALUE) \
> + values.quick_push (string_int_pair ("VXRM_" #NAME, VALUE));
> +#include "riscv-vector-builtins.def"
> +#undef DEF_RVV_VXRM_ENUM
> +
> + lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM",
> +&values); }
> +
> /* Implement #pragma riscv intrinsic vector. */ void
> handle_pragma_vector () @@ -3755,6 +3768,9 @@ handle_pragma_vector ()
> for (unsigned int type_i = 0; type_i < NUM_VECTOR_TYPES; ++type_i)
> register_vector_type ((enum vector_type_index) type_i);
>
> + /* Define the enums. */
> + register_vxrm ();
> +
> /* Define the functions. */
> function_table = new hash_table<registered_function_hasher> (1023);
> function_builder builder;
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def
> b/gcc/config/riscv/riscv-vector-builtins.def
> index 0a387fd1617..2a1a9dbc903 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -83,6 +83,11 @@ along with GCC; see the file COPYING3. If not see
> X64_VLMUL_EXT, TUPLE_SUBPART)
> #endif
>
> +/* Define RVV_VXRM rounding mode enum for fixed-point intrinsics. */
> +#ifndef DEF_RVV_VXRM_ENUM #define DEF_RVV_VXRM_ENUM(NAME, VALUE)
> +#endif
> +
> /* SEW/LMUL = 64:
> Only enable when TARGET_MIN_VLEN > 32.
> Machine mode = VNx1BImode when TARGET_MIN_VLEN < 128.
> @@ -643,6 +648,11 @@ DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type
> (type_idx)) DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type
> (size_type_node)) DEF_RVV_BASE_TYPE (tuple_subpart,
> get_tuple_subpart_type (type_idx))
>
> +DEF_RVV_VXRM_ENUM (RNU, VXRM_RNU)
> +DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE)
> +DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN)
> +DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
> +
> #include "riscv-vector-type-indexer.gen.def"
>
> #undef DEF_RVV_PRED_TYPE
> @@ -651,3 +661,4 @@ DEF_RVV_BASE_TYPE (tuple_subpart,
> get_tuple_subpart_type (type_idx)) #undef DEF_RVV_TUPLE_TYPE #undef
> DEF_RVV_BASE_TYPE #undef DEF_RVV_TYPE_INDEX
> +#undef DEF_RVV_VXRM_ENUM
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
> new file mode 100644
> index 00000000000..0d364787ad0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +size_t f0 ()
> +{
> + return VXRM_RNU;
> +}
> +
> +size_t f1 ()
> +{
> + return VXRM_RNE;
> +}
> +
> +size_t f2 ()
> +{
> + return VXRM_RDN;
> +}
> +
> +size_t f3 ()
> +{
> + return VXRM_ROD;
> +}
> +
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-05-17 1:51 [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics juzhe.zhong
2023-05-17 3:01 ` Kito Cheng
2023-05-17 14:56 ` Li, Pan2
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