* [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
@ 2023-12-12 8:28 pan2.li
2023-12-12 8:30 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2023-12-12 8:28 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to disable the avl propagation for the follow
reasons.
According to the ISA, the first vl elements of vector register
group vs2 should be extracted and packed for vcompress. And the
highest element of vs2 vector may be touched by the mask, which
may be eliminated by avl propagation.
For example, given original vl = 4 here. We have:
v0 = 0b1000
v1 = {0x1, 0x2, 0x3, 0x4}
v2 = {0x5, 0x6, 0x7, 0x8}
Then:
vcompress v1, v2, v0 (avl = 4), v1 = {0x8, 0x2, 0x3, 0x4}. <== Correct.
vcompress v1, v2, v0 (avl = 2), v1 will be unchanged. <== Wrong.
Finally, we cannot propagate avl of vcompress because it may has
senmatics change to the result.
This patch also fix the failure of gcc.c-torture/execute/990128-1.c for
the following configurations.
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
gcc/ChangeLog:
* config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p):
Disable the avl propogation for the vcompress.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/riscv-avlprop.cc | 35 ++++++++++++------
.../rvv/autovec/binop/vcompress-avlprop-1.c | 36 +++++++++++++++++++
2 files changed, 61 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc
index 02f006742f1..a6159816cf7 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -113,19 +113,34 @@ avl_can_be_propagated_p (rtx_insn *rinsn)
touching the element with i > AVL. So, we don't do AVL propagation
on these following situations:
- - The index of "vrgather dest, source, index" may pick up the
- element which has index >= AVL, so we can't strip the elements
- that has index >= AVL of source register.
- - The last element of vslide1down is AVL + 1 according to RVV ISA:
- vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled
- - The last multiple elements of vslidedown can be the element
- has index >= AVL according to RVV ISA:
- 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET]
- vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled. */
+ vgather:
+ - The index of "vrgather dest, source, index" may pick up the
+ element which has index >= AVL, so we can't strip the elements
+ that has index >= AVL of source register.
+ vslide1down:
+ - The last element of vslide1down is AVL + 1 according to RVV ISA:
+ vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled
+ - The last multiple elements of vslidedown can be the element
+ has index >= AVL according to RVV ISA:
+ 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET]
+ vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled.
+ vcompress:
+ - According to the ISA, the first vl elements of vector register
+ group vs2 should be extracted and packed for vcompress. And the
+ highest element of vs2 vector may be touched by the mask. For
+ example, given vlmax = 4 here.
+ v0 = 0b1000
+ v1 = {0x1, 0x2, 0x3, 0x4}
+ v2 = {0x5, 0x6, 0x7, 0x8}
+ vcompress v1, v2, v0 with avl = 4, v1 = {0x8, 0x2, 0x3, 0x4}.
+ vcompress v1, v2, v0 with avl = 2, v1 will be unchanged.
+ Thus, we cannot propagate avl of vcompress because it may has
+ senmatics change to the result. */
return get_attr_type (rinsn) != TYPE_VGATHER
&& get_attr_type (rinsn) != TYPE_VSLIDEDOWN
&& get_attr_type (rinsn) != TYPE_VISLIDE1DOWN
- && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN;
+ && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN
+ && get_attr_type (rinsn) != TYPE_VCOMPRESS;
}
static bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
new file mode 100644
index 00000000000..43f79fe3b7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#define MAX 10
+
+struct s { struct s *n; } *p;
+struct s ss;
+struct s sss[MAX];
+
+/*
+** build_linked_list:
+** ...
+** vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+** vcompress\.vm\s+v[0-9]+,\s*v[0-9]+,\s*v0
+** ...
+** vcompress\.vm\s+v[0-9]+,\s*v[0-9]+,\s*v0
+** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+*/
+void
+build_linked_list ()
+{
+ int i;
+ struct s *next;
+
+ p = &ss;
+ next = p;
+
+ for (i = 0; i < MAX; i++) {
+ next->n = &sss[i];
+ next = next->n;
+ }
+
+ next->n = 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
2023-12-12 8:28 [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation pan2.li
@ 2023-12-12 8:30 ` juzhe.zhong
2023-12-12 8:33 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-12-12 8:30 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 7941 bytes --]
lgtm.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-12-12 16:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
From: Pan Li <pan2.li@intel.com>
This patch would like to disable the avl propagation for the follow
reasons.
According to the ISA, the first vl elements of vector register
group vs2 should be extracted and packed for vcompress. And the
highest element of vs2 vector may be touched by the mask, which
may be eliminated by avl propagation.
For example, given original vl = 4 here. We have:
v0 = 0b1000
v1 = {0x1, 0x2, 0x3, 0x4}
v2 = {0x5, 0x6, 0x7, 0x8}
Then:
vcompress v1, v2, v0 (avl = 4), v1 = {0x8, 0x2, 0x3, 0x4}. <== Correct.
vcompress v1, v2, v0 (avl = 2), v1 will be unchanged. <== Wrong.
Finally, we cannot propagate avl of vcompress because it may has
senmatics change to the result.
This patch also fix the failure of gcc.c-torture/execute/990128-1.c for
the following configurations.
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
gcc/ChangeLog:
* config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p):
Disable the avl propogation for the vcompress.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/riscv-avlprop.cc | 35 ++++++++++++------
.../rvv/autovec/binop/vcompress-avlprop-1.c | 36 +++++++++++++++++++
2 files changed, 61 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc
index 02f006742f1..a6159816cf7 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -113,19 +113,34 @@ avl_can_be_propagated_p (rtx_insn *rinsn)
touching the element with i > AVL. So, we don't do AVL propagation
on these following situations:
- - The index of "vrgather dest, source, index" may pick up the
- element which has index >= AVL, so we can't strip the elements
- that has index >= AVL of source register.
- - The last element of vslide1down is AVL + 1 according to RVV ISA:
- vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled
- - The last multiple elements of vslidedown can be the element
- has index >= AVL according to RVV ISA:
- 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET]
- vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled. */
+ vgather:
+ - The index of "vrgather dest, source, index" may pick up the
+ element which has index >= AVL, so we can't strip the elements
+ that has index >= AVL of source register.
+ vslide1down:
+ - The last element of vslide1down is AVL + 1 according to RVV ISA:
+ vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled
+ - The last multiple elements of vslidedown can be the element
+ has index >= AVL according to RVV ISA:
+ 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET]
+ vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled.
+ vcompress:
+ - According to the ISA, the first vl elements of vector register
+ group vs2 should be extracted and packed for vcompress. And the
+ highest element of vs2 vector may be touched by the mask. For
+ example, given vlmax = 4 here.
+ v0 = 0b1000
+ v1 = {0x1, 0x2, 0x3, 0x4}
+ v2 = {0x5, 0x6, 0x7, 0x8}
+ vcompress v1, v2, v0 with avl = 4, v1 = {0x8, 0x2, 0x3, 0x4}.
+ vcompress v1, v2, v0 with avl = 2, v1 will be unchanged.
+ Thus, we cannot propagate avl of vcompress because it may has
+ senmatics change to the result. */
return get_attr_type (rinsn) != TYPE_VGATHER
&& get_attr_type (rinsn) != TYPE_VSLIDEDOWN
&& get_attr_type (rinsn) != TYPE_VISLIDE1DOWN
- && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN;
+ && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN
+ && get_attr_type (rinsn) != TYPE_VCOMPRESS;
}
static bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
new file mode 100644
index 00000000000..43f79fe3b7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#define MAX 10
+
+struct s { struct s *n; } *p;
+struct s ss;
+struct s sss[MAX];
+
+/*
+** build_linked_list:
+** ...
+** vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+** vcompress\.vm\s+v[0-9]+,\s*v[0-9]+,\s*v0
+** ...
+** vcompress\.vm\s+v[0-9]+,\s*v[0-9]+,\s*v0
+** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+*/
+void
+build_linked_list ()
+{
+ int i;
+ struct s *next;
+
+ p = &ss;
+ next = p;
+
+ for (i = 0; i < MAX; i++) {
+ next->n = &sss[i];
+ next = next->n;
+ }
+
+ next->n = 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
2023-12-12 8:30 ` juzhe.zhong
@ 2023-12-12 8:33 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-12-12 8:33 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 8593 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Tuesday, December 12, 2023 4:30 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
lgtm.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-12-12 16:28
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to disable the avl propagation for the follow
reasons.
According to the ISA, the first vl elements of vector register
group vs2 should be extracted and packed for vcompress. And the
highest element of vs2 vector may be touched by the mask, which
may be eliminated by avl propagation.
For example, given original vl = 4 here. We have:
v0 = 0b1000
v1 = {0x1, 0x2, 0x3, 0x4}
v2 = {0x5, 0x6, 0x7, 0x8}
Then:
vcompress v1, v2, v0 (avl = 4), v1 = {0x8, 0x2, 0x3, 0x4}. <== Correct.
vcompress v1, v2, v0 (avl = 2), v1 will be unchanged. <== Wrong.
Finally, we cannot propagate avl of vcompress because it may has
senmatics change to the result.
This patch also fix the failure of gcc.c-torture/execute/990128-1.c for
the following configurations.
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8
riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
gcc/ChangeLog:
* config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p):
Disable the avl propogation for the vcompress.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/config/riscv/riscv-avlprop.cc | 35 ++++++++++++------
.../rvv/autovec/binop/vcompress-avlprop-1.c | 36 +++++++++++++++++++
2 files changed, 61 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc
index 02f006742f1..a6159816cf7 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -113,19 +113,34 @@ avl_can_be_propagated_p (rtx_insn *rinsn)
touching the element with i > AVL. So, we don't do AVL propagation
on these following situations:
- - The index of "vrgather dest, source, index" may pick up the
- element which has index >= AVL, so we can't strip the elements
- that has index >= AVL of source register.
- - The last element of vslide1down is AVL + 1 according to RVV ISA:
- vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled
- - The last multiple elements of vslidedown can be the element
- has index >= AVL according to RVV ISA:
- 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET]
- vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled. */
+ vgather:
+ - The index of "vrgather dest, source, index" may pick up the
+ element which has index >= AVL, so we can't strip the elements
+ that has index >= AVL of source register.
+ vslide1down:
+ - The last element of vslide1down is AVL + 1 according to RVV ISA:
+ vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled
+ - The last multiple elements of vslidedown can be the element
+ has index >= AVL according to RVV ISA:
+ 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET]
+ vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled.
+ vcompress:
+ - According to the ISA, the first vl elements of vector register
+ group vs2 should be extracted and packed for vcompress. And the
+ highest element of vs2 vector may be touched by the mask. For
+ example, given vlmax = 4 here.
+ v0 = 0b1000
+ v1 = {0x1, 0x2, 0x3, 0x4}
+ v2 = {0x5, 0x6, 0x7, 0x8}
+ vcompress v1, v2, v0 with avl = 4, v1 = {0x8, 0x2, 0x3, 0x4}.
+ vcompress v1, v2, v0 with avl = 2, v1 will be unchanged.
+ Thus, we cannot propagate avl of vcompress because it may has
+ senmatics change to the result. */
return get_attr_type (rinsn) != TYPE_VGATHER
&& get_attr_type (rinsn) != TYPE_VSLIDEDOWN
&& get_attr_type (rinsn) != TYPE_VISLIDE1DOWN
- && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN;
+ && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN
+ && get_attr_type (rinsn) != TYPE_VCOMPRESS;
}
static bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
new file mode 100644
index 00000000000..43f79fe3b7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#define MAX 10
+
+struct s { struct s *n; } *p;
+struct s ss;
+struct s sss[MAX];
+
+/*
+** build_linked_list:
+** ...
+** vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+** vcompress\.vm\s+v[0-9]+,\s*v[0-9]+,\s*v0
+** ...
+** vcompress\.vm\s+v[0-9]+,\s*v[0-9]+,\s*v0
+** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+*/
+void
+build_linked_list ()
+{
+ int i;
+ struct s *next;
+
+ p = &ss;
+ next = p;
+
+ for (i = 0; i < MAX; i++) {
+ next->n = &sss[i];
+ next = next->n;
+ }
+
+ next->n = 0;
+}
--
2.34.1
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2023-12-12 8:28 [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation pan2.li
2023-12-12 8:30 ` juzhe.zhong
2023-12-12 8:33 ` Li, Pan2
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