* [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
@ 2024-04-20 15:21 pan2.li
2024-04-20 23:58 ` 钟居哲
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2024-04-20 15:21 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
We reverted below patch for register group overlap, add the related
insn test and mark it as xfail. And we will remove the xfail
after we support the register overlap in GCC-15.
018ba3ac952 RISC-V: Fix overlap group incorrect overlap on v0
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-34.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/base/pr112431-34.c | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
new file mode 100644
index 00000000000..286185aa01e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
@@ -0,0 +1,101 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
+ size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
+ size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
+ size_t sum15)
+{
+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9
+ + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
+}
+
+size_t
+foo (char const *buf, size_t len)
+{
+ size_t sum = 0;
+ size_t vl = __riscv_vsetvlmax_e8m8 ();
+ size_t step = vl * 4;
+ const char *it = buf, *end = buf + len;
+ for (; it + step <= end;)
+ {
+ vuint8m1_t v0 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v1 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v2 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v3 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v4 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v5 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v6 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v7 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v8 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v9 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v10 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v11 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v12 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v13 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v14 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v15 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+
+ asm volatile("nop" ::: "memory");
+ vint16m2_t vw0 = __riscv_vluxei8_v_i16m2 ((void *) it, v0, vl);
+ vint16m2_t vw1 = __riscv_vluxei8_v_i16m2 ((void *) it, v1, vl);
+ vint16m2_t vw2 = __riscv_vluxei8_v_i16m2 ((void *) it, v2, vl);
+ vint16m2_t vw3 = __riscv_vluxei8_v_i16m2 ((void *) it, v3, vl);
+ vint16m2_t vw4 = __riscv_vluxei8_v_i16m2 ((void *) it, v4, vl);
+ vint16m2_t vw5 = __riscv_vluxei8_v_i16m2 ((void *) it, v5, vl);
+ vint16m2_t vw6 = __riscv_vluxei8_v_i16m2 ((void *) it, v6, vl);
+ vint16m2_t vw7 = __riscv_vluxei8_v_i16m2 ((void *) it, v7, vl);
+ vint16m2_t vw8 = __riscv_vluxei8_v_i16m2 ((void *) it, v8, vl);
+ vint16m2_t vw9 = __riscv_vluxei8_v_i16m2 ((void *) it, v9, vl);
+ vint16m2_t vw10 = __riscv_vluxei8_v_i16m2 ((void *) it, v10, vl);
+ vint16m2_t vw11 = __riscv_vluxei8_v_i16m2 ((void *) it, v11, vl);
+ vint16m2_t vw12 = __riscv_vluxei8_v_i16m2 ((void *) it, v12, vl);
+ vint16m2_t vw13 = __riscv_vluxei8_v_i16m2 ((void *) it, v13, vl);
+ vint16m2_t vw14 = __riscv_vluxei8_v_i16m2 ((void *) it, v14, vl);
+ vbool8_t mask = *(vbool8_t*)it;
+ vint16m2_t vw15 = __riscv_vluxei8_v_i16m2_m (mask, (void *) it, v15, vl);
+
+ asm volatile("nop" ::: "memory");
+ size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
+ size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);
+ size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2);
+ size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3);
+ size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4);
+ size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5);
+ size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6);
+ size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7);
+ size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8);
+ size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9);
+ size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10);
+ size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11);
+ size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12);
+ size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13);
+ size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14);
+ size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15);
+
+ sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8,
+ sum9, sum10, sum11, sum12, sum13, sum14, sum15);
+ }
+ return sum;
+}
+
+/* { dg-final { scan-assembler-not {vluxei8\.v\tv0,\s*\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} { xfail riscv*-*-* } } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
2024-04-20 15:21 [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0 pan2.li
@ 2024-04-20 23:58 ` 钟居哲
2024-04-21 1:36 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: 钟居哲 @ 2024-04-20 23:58 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, rdapp.gcc, pan2.li
[-- Attachment #1: Type: text/plain, Size: 5739 bytes --]
lgtm
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-04-20 23:21
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
From: Pan Li <pan2.li@intel.com>
We reverted below patch for register group overlap, add the related
insn test and mark it as xfail. And we will remove the xfail
after we support the register overlap in GCC-15.
018ba3ac952 RISC-V: Fix overlap group incorrect overlap on v0
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-34.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/base/pr112431-34.c | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
new file mode 100644
index 00000000000..286185aa01e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
@@ -0,0 +1,101 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
+ size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
+ size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
+ size_t sum15)
+{
+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9
+ + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
+}
+
+size_t
+foo (char const *buf, size_t len)
+{
+ size_t sum = 0;
+ size_t vl = __riscv_vsetvlmax_e8m8 ();
+ size_t step = vl * 4;
+ const char *it = buf, *end = buf + len;
+ for (; it + step <= end;)
+ {
+ vuint8m1_t v0 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v1 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v2 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v3 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v4 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v5 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v6 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v7 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v8 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v9 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v10 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v11 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v12 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v13 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v14 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v15 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+
+ asm volatile("nop" ::: "memory");
+ vint16m2_t vw0 = __riscv_vluxei8_v_i16m2 ((void *) it, v0, vl);
+ vint16m2_t vw1 = __riscv_vluxei8_v_i16m2 ((void *) it, v1, vl);
+ vint16m2_t vw2 = __riscv_vluxei8_v_i16m2 ((void *) it, v2, vl);
+ vint16m2_t vw3 = __riscv_vluxei8_v_i16m2 ((void *) it, v3, vl);
+ vint16m2_t vw4 = __riscv_vluxei8_v_i16m2 ((void *) it, v4, vl);
+ vint16m2_t vw5 = __riscv_vluxei8_v_i16m2 ((void *) it, v5, vl);
+ vint16m2_t vw6 = __riscv_vluxei8_v_i16m2 ((void *) it, v6, vl);
+ vint16m2_t vw7 = __riscv_vluxei8_v_i16m2 ((void *) it, v7, vl);
+ vint16m2_t vw8 = __riscv_vluxei8_v_i16m2 ((void *) it, v8, vl);
+ vint16m2_t vw9 = __riscv_vluxei8_v_i16m2 ((void *) it, v9, vl);
+ vint16m2_t vw10 = __riscv_vluxei8_v_i16m2 ((void *) it, v10, vl);
+ vint16m2_t vw11 = __riscv_vluxei8_v_i16m2 ((void *) it, v11, vl);
+ vint16m2_t vw12 = __riscv_vluxei8_v_i16m2 ((void *) it, v12, vl);
+ vint16m2_t vw13 = __riscv_vluxei8_v_i16m2 ((void *) it, v13, vl);
+ vint16m2_t vw14 = __riscv_vluxei8_v_i16m2 ((void *) it, v14, vl);
+ vbool8_t mask = *(vbool8_t*)it;
+ vint16m2_t vw15 = __riscv_vluxei8_v_i16m2_m (mask, (void *) it, v15, vl);
+
+ asm volatile("nop" ::: "memory");
+ size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
+ size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);
+ size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2);
+ size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3);
+ size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4);
+ size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5);
+ size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6);
+ size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7);
+ size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8);
+ size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9);
+ size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10);
+ size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11);
+ size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12);
+ size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13);
+ size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14);
+ size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15);
+
+ sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8,
+ sum9, sum10, sum11, sum12, sum13, sum14, sum15);
+ }
+ return sum;
+}
+
+/* { dg-final { scan-assembler-not {vluxei8\.v\tv0,\s*\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} { xfail riscv*-*-* } } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
2024-04-20 23:58 ` 钟居哲
@ 2024-04-21 1:36 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2024-04-21 1:36 UTC (permalink / raw)
To: 钟居哲, gcc-patches; +Cc: kito.cheng, rdapp.gcc
[-- Attachment #1: Type: text/plain, Size: 6374 bytes --]
Committed, thanks Juzhe.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Sunday, April 21, 2024 7:59 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; rdapp.gcc <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
lgtm
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2024-04-20 23:21
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@gmail.com>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; Pan Li<mailto:pan2.li@intel.com>
Subject: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
We reverted below patch for register group overlap, add the related
insn test and mark it as xfail. And we will remove the xfail
after we support the register overlap in GCC-15.
018ba3ac952 RISC-V: Fix overlap group incorrect overlap on v0
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-34.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
.../gcc.target/riscv/rvv/base/pr112431-34.c | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
new file mode 100644
index 00000000000..286185aa01e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c
@@ -0,0 +1,101 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
+ size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
+ size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
+ size_t sum15)
+{
+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9
+ + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
+}
+
+size_t
+foo (char const *buf, size_t len)
+{
+ size_t sum = 0;
+ size_t vl = __riscv_vsetvlmax_e8m8 ();
+ size_t step = vl * 4;
+ const char *it = buf, *end = buf + len;
+ for (; it + step <= end;)
+ {
+ vuint8m1_t v0 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v1 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v2 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v3 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v4 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v5 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v6 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v7 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v8 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v9 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v10 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v11 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v12 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v13 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v14 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+ vuint8m1_t v15 = __riscv_vle8_v_u8m1 ((void *) it, vl);
+ it += vl;
+
+ asm volatile("nop" ::: "memory");
+ vint16m2_t vw0 = __riscv_vluxei8_v_i16m2 ((void *) it, v0, vl);
+ vint16m2_t vw1 = __riscv_vluxei8_v_i16m2 ((void *) it, v1, vl);
+ vint16m2_t vw2 = __riscv_vluxei8_v_i16m2 ((void *) it, v2, vl);
+ vint16m2_t vw3 = __riscv_vluxei8_v_i16m2 ((void *) it, v3, vl);
+ vint16m2_t vw4 = __riscv_vluxei8_v_i16m2 ((void *) it, v4, vl);
+ vint16m2_t vw5 = __riscv_vluxei8_v_i16m2 ((void *) it, v5, vl);
+ vint16m2_t vw6 = __riscv_vluxei8_v_i16m2 ((void *) it, v6, vl);
+ vint16m2_t vw7 = __riscv_vluxei8_v_i16m2 ((void *) it, v7, vl);
+ vint16m2_t vw8 = __riscv_vluxei8_v_i16m2 ((void *) it, v8, vl);
+ vint16m2_t vw9 = __riscv_vluxei8_v_i16m2 ((void *) it, v9, vl);
+ vint16m2_t vw10 = __riscv_vluxei8_v_i16m2 ((void *) it, v10, vl);
+ vint16m2_t vw11 = __riscv_vluxei8_v_i16m2 ((void *) it, v11, vl);
+ vint16m2_t vw12 = __riscv_vluxei8_v_i16m2 ((void *) it, v12, vl);
+ vint16m2_t vw13 = __riscv_vluxei8_v_i16m2 ((void *) it, v13, vl);
+ vint16m2_t vw14 = __riscv_vluxei8_v_i16m2 ((void *) it, v14, vl);
+ vbool8_t mask = *(vbool8_t*)it;
+ vint16m2_t vw15 = __riscv_vluxei8_v_i16m2_m (mask, (void *) it, v15, vl);
+
+ asm volatile("nop" ::: "memory");
+ size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
+ size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);
+ size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2);
+ size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3);
+ size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4);
+ size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5);
+ size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6);
+ size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7);
+ size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8);
+ size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9);
+ size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10);
+ size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11);
+ size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12);
+ size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13);
+ size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14);
+ size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15);
+
+ sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8,
+ sum9, sum10, sum11, sum12, sum13, sum14, sum15);
+ }
+ return sum;
+}
+
+/* { dg-final { scan-assembler-not {vluxei8\.v\tv0,\s*\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} { xfail riscv*-*-* } } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-04-21 1:36 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-20 15:21 [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0 pan2.li
2024-04-20 23:58 ` 钟居哲
2024-04-21 1:36 ` Li, Pan2
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).