* [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
@ 2023-08-10 8:19 pan2.li
2023-08-10 8:54 ` Kito Cheng
0 siblings, 1 reply; 6+ messages in thread
From: pan2.li @ 2023-08-10 8:19 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmacc_frm): New class for vfnmacc.
(vfnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmacc_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-nmacc.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++++++++++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-nmacc.c | 47 +++++++++++++++++++
4 files changed, 74 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1695d77e8bd..1d4a5a18bf9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -379,6 +379,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmacc
+*/
+class vfnmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander &e) const override
+ {
+ if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
+ if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
+ gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
+static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
@@ -2380,6 +2403,7 @@ BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
+BASE (vfnmacc_frm)
BASE (vfmsac)
BASE (vfnmadd)
BASE (vfmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 67d18412b4c..247074d0868 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
+extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 92ecf8a9065..7aae0665520 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -351,6 +351,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
new file mode 100644
index 00000000000..fca378b7a8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1 (vd, op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfnmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
2023-08-10 8:19 [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API pan2.li
@ 2023-08-10 8:54 ` Kito Cheng
2023-08-10 12:39 ` Li, Pan2
0 siblings, 1 reply; 6+ messages in thread
From: Kito Cheng @ 2023-08-10 8:54 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, jeffreyalaw, yanzhang.wang
LGTM
On Thu, Aug 10, 2023 at 4:20 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to support the rounding mode API for the
> VFNMACC for the below samples.
>
> * __riscv_vfnmacc_vv_f32m1_rm
> * __riscv_vfnmacc_vv_f32m1_rm_m
> * __riscv_vfnmacc_vf_f32m1_rm
> * __riscv_vfnmacc_vf_f32m1_rm_m
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (class vfnmacc_frm): New class for vfnmacc.
> (vfnmacc_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfnmacc_frm): New function definition.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-nmacc.c: New test.
> ---
> .../riscv/riscv-vector-builtins-bases.cc | 24 ++++++++++
> .../riscv/riscv-vector-builtins-bases.h | 1 +
> .../riscv/riscv-vector-builtins-functions.def | 2 +
> .../riscv/rvv/base/float-point-nmacc.c | 47 +++++++++++++++++++
> 4 files changed, 74 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 1695d77e8bd..1d4a5a18bf9 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -379,6 +379,28 @@ public:
> }
> };
>
> +/* Implements below instructions for frm
> + - vfnmacc
> +*/
> +class vfnmacc_frm : public function_base
> +{
> +public:
> + bool has_rounding_mode_operand_p () const override { return true; }
> +
> + bool has_merge_operand_p () const override { return false; }
> +
> + rtx expand (function_expander &e) const override
> + {
> + if (e.op_info->op == OP_TYPE_vf)
> + return e.use_ternop_insn (
> + true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
> + if (e.op_info->op == OP_TYPE_vv)
> + return e.use_ternop_insn (
> + true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
> + gcc_unreachable ();
> + }
> +};
> +
> /* Implements vrsub. */
> class vrsub : public function_base
> {
> @@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
> static CONSTEXPR const vfmadd vfmadd_obj;
> static CONSTEXPR const vfnmsub vfnmsub_obj;
> static CONSTEXPR const vfnmacc vfnmacc_obj;
> +static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
> static CONSTEXPR const vfmsac vfmsac_obj;
> static CONSTEXPR const vfnmadd vfnmadd_obj;
> static CONSTEXPR const vfmsub vfmsub_obj;
> @@ -2380,6 +2403,7 @@ BASE (vfnmsac)
> BASE (vfmadd)
> BASE (vfnmsub)
> BASE (vfnmacc)
> +BASE (vfnmacc_frm)
> BASE (vfmsac)
> BASE (vfnmadd)
> BASE (vfmsub)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index 67d18412b4c..247074d0868 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
> extern const function_base *const vfmadd;
> extern const function_base *const vfnmsub;
> extern const function_base *const vfnmacc;
> +extern const function_base *const vfnmacc_frm;
> extern const function_base *const vfmsac;
> extern const function_base *const vfnmadd;
> extern const function_base *const vfmsub;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 92ecf8a9065..7aae0665520 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -351,6 +351,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
>
> DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
> DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
> +DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
> +DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
>
> // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
> DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
> new file mode 100644
> index 00000000000..fca378b7a8f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef float float32_t;
> +
> +vfloat32m1_t
> +test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
> + size_t vl) {
> + return __riscv_vfnmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfnmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1 (vd, op1, op2, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vfnmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
2023-08-10 8:54 ` Kito Cheng
@ 2023-08-10 12:39 ` Li, Pan2
0 siblings, 0 replies; 6+ messages in thread
From: Li, Pan2 @ 2023-08-10 12:39 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, jeffreyalaw, Wang, Yanzhang
Committed, thanks Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Thursday, August 10, 2023 4:54 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
LGTM
On Thu, Aug 10, 2023 at 4:20 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to support the rounding mode API for the
> VFNMACC for the below samples.
>
> * __riscv_vfnmacc_vv_f32m1_rm
> * __riscv_vfnmacc_vv_f32m1_rm_m
> * __riscv_vfnmacc_vf_f32m1_rm
> * __riscv_vfnmacc_vf_f32m1_rm_m
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (class vfnmacc_frm): New class for vfnmacc.
> (vfnmacc_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfnmacc_frm): New function definition.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-nmacc.c: New test.
> ---
> .../riscv/riscv-vector-builtins-bases.cc | 24 ++++++++++
> .../riscv/riscv-vector-builtins-bases.h | 1 +
> .../riscv/riscv-vector-builtins-functions.def | 2 +
> .../riscv/rvv/base/float-point-nmacc.c | 47 +++++++++++++++++++
> 4 files changed, 74 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 1695d77e8bd..1d4a5a18bf9 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -379,6 +379,28 @@ public:
> }
> };
>
> +/* Implements below instructions for frm
> + - vfnmacc
> +*/
> +class vfnmacc_frm : public function_base
> +{
> +public:
> + bool has_rounding_mode_operand_p () const override { return true; }
> +
> + bool has_merge_operand_p () const override { return false; }
> +
> + rtx expand (function_expander &e) const override
> + {
> + if (e.op_info->op == OP_TYPE_vf)
> + return e.use_ternop_insn (
> + true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
> + if (e.op_info->op == OP_TYPE_vv)
> + return e.use_ternop_insn (
> + true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
> + gcc_unreachable ();
> + }
> +};
> +
> /* Implements vrsub. */
> class vrsub : public function_base
> {
> @@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
> static CONSTEXPR const vfmadd vfmadd_obj;
> static CONSTEXPR const vfnmsub vfnmsub_obj;
> static CONSTEXPR const vfnmacc vfnmacc_obj;
> +static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
> static CONSTEXPR const vfmsac vfmsac_obj;
> static CONSTEXPR const vfnmadd vfnmadd_obj;
> static CONSTEXPR const vfmsub vfmsub_obj;
> @@ -2380,6 +2403,7 @@ BASE (vfnmsac)
> BASE (vfmadd)
> BASE (vfnmsub)
> BASE (vfnmacc)
> +BASE (vfnmacc_frm)
> BASE (vfmsac)
> BASE (vfnmadd)
> BASE (vfmsub)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index 67d18412b4c..247074d0868 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
> extern const function_base *const vfmadd;
> extern const function_base *const vfnmsub;
> extern const function_base *const vfnmacc;
> +extern const function_base *const vfnmacc_frm;
> extern const function_base *const vfmsac;
> extern const function_base *const vfnmadd;
> extern const function_base *const vfmsub;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 92ecf8a9065..7aae0665520 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -351,6 +351,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
>
> DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
> DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
> +DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
> +DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
>
> // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
> DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
> new file mode 100644
> index 00000000000..fca378b7a8f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef float float32_t;
> +
> +vfloat32m1_t
> +test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
> + size_t vl) {
> + return __riscv_vfnmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfnmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1 (vd, op1, op2, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
> + vfloat32m1_t op2, size_t vl) {
> + return __riscv_vfnmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vfnmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
2023-08-04 2:23 ` juzhe.zhong
@ 2023-08-04 2:38 ` Li, Pan2
0 siblings, 0 replies; 6+ messages in thread
From: Li, Pan2 @ 2023-08-04 2:38 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 6997 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, August 4, 2023 10:24 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Kito.cheng <kito.cheng@sifive.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
LGTM.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-08-04 10:22
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmacc_frm): New class for vfnmacc.
(vfnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmacc_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c:
New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++++++++++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../float-point-single-negate-multiply-add.c | 47 +++++++++++++++++++
4 files changed, 74 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1695d77e8bd..1d4a5a18bf9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -379,6 +379,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmacc
+*/
+class vfnmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander &e) const override
+ {
+ if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
+ if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
+ gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
+static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
@@ -2380,6 +2403,7 @@ BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
+BASE (vfnmacc_frm)
BASE (vfmsac)
BASE (vfnmadd)
BASE (vfmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 67d18412b4c..247074d0868 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
+extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 3906f2e6248..223e8346cd8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -350,6 +350,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvvv_ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
new file mode 100644
index 00000000000..fca378b7a8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1 (vd, op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfnmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
2023-08-04 2:22 pan2.li
@ 2023-08-04 2:23 ` juzhe.zhong
2023-08-04 2:38 ` Li, Pan2
0 siblings, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-08-04 2:23 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: Kito.cheng, pan2.li, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 6330 bytes --]
LGTM.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-08-04 10:22
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
From: Pan Li <pan2.li@intel.com>
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmacc_frm): New class for vfnmacc.
(vfnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmacc_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c:
New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++++++++++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../float-point-single-negate-multiply-add.c | 47 +++++++++++++++++++
4 files changed, 74 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1695d77e8bd..1d4a5a18bf9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -379,6 +379,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmacc
+*/
+class vfnmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander &e) const override
+ {
+ if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
+ if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
+ gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
+static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
@@ -2380,6 +2403,7 @@ BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
+BASE (vfnmacc_frm)
BASE (vfmsac)
BASE (vfnmadd)
BASE (vfmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 67d18412b4c..247074d0868 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
+extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 3906f2e6248..223e8346cd8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -350,6 +350,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvvv_ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
new file mode 100644
index 00000000000..fca378b7a8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1 (vd, op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfnmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
@ 2023-08-04 2:22 pan2.li
2023-08-04 2:23 ` juzhe.zhong
0 siblings, 1 reply; 6+ messages in thread
From: pan2.li @ 2023-08-04 2:22 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmacc_frm): New class for vfnmacc.
(vfnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmacc_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c:
New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++++++++++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../float-point-single-negate-multiply-add.c | 47 +++++++++++++++++++
4 files changed, 74 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1695d77e8bd..1d4a5a18bf9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -379,6 +379,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmacc
+*/
+class vfnmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander &e) const override
+ {
+ if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
+ if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
+ gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
+static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
@@ -2380,6 +2403,7 @@ BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
+BASE (vfnmacc_frm)
BASE (vfmsac)
BASE (vfnmadd)
BASE (vfmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 67d18412b4c..247074d0868 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
+extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 3906f2e6248..223e8346cd8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -350,6 +350,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvvv_ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
new file mode 100644
index 00000000000..fca378b7a8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1 (vd, op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfnmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
--
2.34.1
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2023-08-10 8:19 [PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API pan2.li
2023-08-10 8:54 ` Kito Cheng
2023-08-10 12:39 ` Li, Pan2
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2023-08-04 2:22 pan2.li
2023-08-04 2:23 ` juzhe.zhong
2023-08-04 2:38 ` Li, Pan2
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