* [PATCH] RISC-V: Refactor the or pattern to switch cases
@ 2023-05-14 8:21 pan2.li
2023-05-14 8:44 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2023-05-14 8:21 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch refactor the pattern A or B or C or D, to the switch case for
easy add/remove new types, as well as human reading friendly.
Before this patch:
return A || B || C || D;
After this patch:
switch (type)
{
case A:
case B:
case C:
case D:
return true;
default:
return false;
}
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (required_extensions_p):
Refactor the or pattern to switch cases.
---
gcc/config/riscv/riscv-vector-builtins.cc | 37 ++++++++++++++++-------
1 file changed, 26 insertions(+), 11 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 4117897c6c9..0f56f29f7aa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2606,17 +2606,32 @@ register_vector_type (vector_type_index type)
static bool
required_extensions_p (enum rvv_base_type type)
{
- return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index
- || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index
- || type == RVV_BASE_float_vector
- || type == RVV_BASE_double_trunc_float_vector
- || type == RVV_BASE_double_trunc_vector
- || type == RVV_BASE_widen_lmul1_vector
- || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret
- || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret
- || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4
- || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16
- || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64;
+ switch (type)
+ {
+ case RVV_BASE_eew8_index:
+ case RVV_BASE_eew16_index:
+ case RVV_BASE_eew32_index:
+ case RVV_BASE_eew64_index:
+ case RVV_BASE_float_vector:
+ case RVV_BASE_double_trunc_float_vector:
+ case RVV_BASE_double_trunc_vector:
+ case RVV_BASE_widen_lmul1_vector:
+ case RVV_BASE_eew8_interpret:
+ case RVV_BASE_eew16_interpret:
+ case RVV_BASE_eew32_interpret:
+ case RVV_BASE_eew64_interpret:
+ case RVV_BASE_vlmul_ext_x2:
+ case RVV_BASE_vlmul_ext_x4:
+ case RVV_BASE_vlmul_ext_x8:
+ case RVV_BASE_vlmul_ext_x16:
+ case RVV_BASE_vlmul_ext_x32:
+ case RVV_BASE_vlmul_ext_x64:
+ return true;
+ default:
+ return false;
+ }
+
+ gcc_unreachable ();
}
static uint64_t
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Refactor the or pattern to switch cases
2023-05-14 8:21 [PATCH] RISC-V: Refactor the or pattern to switch cases pan2.li
@ 2023-05-14 8:44 ` Kito Cheng
2023-05-14 9:11 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2023-05-14 8:44 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, kito.cheng, yanzhang.wang
OK, thanks :)
On Sun, May 14, 2023 at 4:22 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch refactor the pattern A or B or C or D, to the switch case for
> easy add/remove new types, as well as human reading friendly.
>
> Before this patch:
> return A || B || C || D;
>
> After this patch:
> switch (type)
> {
> case A:
> case B:
> case C:
> case D:
> return true;
> default:
> return false;
> }
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (required_extensions_p):
> Refactor the or pattern to switch cases.
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 37 ++++++++++++++++-------
> 1 file changed, 26 insertions(+), 11 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 4117897c6c9..0f56f29f7aa 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -2606,17 +2606,32 @@ register_vector_type (vector_type_index type)
> static bool
> required_extensions_p (enum rvv_base_type type)
> {
> - return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index
> - || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index
> - || type == RVV_BASE_float_vector
> - || type == RVV_BASE_double_trunc_float_vector
> - || type == RVV_BASE_double_trunc_vector
> - || type == RVV_BASE_widen_lmul1_vector
> - || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret
> - || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret
> - || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4
> - || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16
> - || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64;
> + switch (type)
> + {
> + case RVV_BASE_eew8_index:
> + case RVV_BASE_eew16_index:
> + case RVV_BASE_eew32_index:
> + case RVV_BASE_eew64_index:
> + case RVV_BASE_float_vector:
> + case RVV_BASE_double_trunc_float_vector:
> + case RVV_BASE_double_trunc_vector:
> + case RVV_BASE_widen_lmul1_vector:
> + case RVV_BASE_eew8_interpret:
> + case RVV_BASE_eew16_interpret:
> + case RVV_BASE_eew32_interpret:
> + case RVV_BASE_eew64_interpret:
> + case RVV_BASE_vlmul_ext_x2:
> + case RVV_BASE_vlmul_ext_x4:
> + case RVV_BASE_vlmul_ext_x8:
> + case RVV_BASE_vlmul_ext_x16:
> + case RVV_BASE_vlmul_ext_x32:
> + case RVV_BASE_vlmul_ext_x64:
> + return true;
> + default:
> + return false;
> + }
> +
> + gcc_unreachable ();
> }
>
> static uint64_t
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] RISC-V: Refactor the or pattern to switch cases
2023-05-14 8:44 ` Kito Cheng
@ 2023-05-14 9:11 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-05-14 9:11 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, kito.cheng, Wang, Yanzhang
Committed, thank you kito!
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Sunday, May 14, 2023 4:45 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: Refactor the or pattern to switch cases
OK, thanks :)
On Sun, May 14, 2023 at 4:22 PM Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch refactor the pattern A or B or C or D, to the switch case
> for easy add/remove new types, as well as human reading friendly.
>
> Before this patch:
> return A || B || C || D;
>
> After this patch:
> switch (type)
> {
> case A:
> case B:
> case C:
> case D:
> return true;
> default:
> return false;
> }
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (required_extensions_p):
> Refactor the or pattern to switch cases.
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 37
> ++++++++++++++++-------
> 1 file changed, 26 insertions(+), 11 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 4117897c6c9..0f56f29f7aa 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -2606,17 +2606,32 @@ register_vector_type (vector_type_index type)
> static bool required_extensions_p (enum rvv_base_type type) {
> - return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index
> - || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index
> - || type == RVV_BASE_float_vector
> - || type == RVV_BASE_double_trunc_float_vector
> - || type == RVV_BASE_double_trunc_vector
> - || type == RVV_BASE_widen_lmul1_vector
> - || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret
> - || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret
> - || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4
> - || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16
> - || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64;
> + switch (type)
> + {
> + case RVV_BASE_eew8_index:
> + case RVV_BASE_eew16_index:
> + case RVV_BASE_eew32_index:
> + case RVV_BASE_eew64_index:
> + case RVV_BASE_float_vector:
> + case RVV_BASE_double_trunc_float_vector:
> + case RVV_BASE_double_trunc_vector:
> + case RVV_BASE_widen_lmul1_vector:
> + case RVV_BASE_eew8_interpret:
> + case RVV_BASE_eew16_interpret:
> + case RVV_BASE_eew32_interpret:
> + case RVV_BASE_eew64_interpret:
> + case RVV_BASE_vlmul_ext_x2:
> + case RVV_BASE_vlmul_ext_x4:
> + case RVV_BASE_vlmul_ext_x8:
> + case RVV_BASE_vlmul_ext_x16:
> + case RVV_BASE_vlmul_ext_x32:
> + case RVV_BASE_vlmul_ext_x64:
> + return true;
> + default:
> + return false;
> + }
> +
> + gcc_unreachable ();
> }
>
> static uint64_t
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-05-14 9:12 UTC | newest]
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2023-05-14 8:21 [PATCH] RISC-V: Refactor the or pattern to switch cases pan2.li
2023-05-14 8:44 ` Kito Cheng
2023-05-14 9:11 ` Li, Pan2
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