* [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
@ 2023-05-25 12:46 pan2.li
2023-05-29 1:31 ` Li, Pan2
2023-05-29 2:24 ` [PATCH v2] " pan2.li
0 siblings, 2 replies; 7+ messages in thread
From: pan2.li @ 2023-05-25 12:46 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to add new sub extension (aka ZVFHMIN) to the
-march= option. To make it simple, only the sub extension itself is
involved in this patch, and the underlying FP16 related RVV intrinsic
API depends on the TARGET_ZVFHMIN.
You can locate more information about ZVFHMIN from below spec doc.
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 3 ++
gcc/config/riscv/riscv-opts.h | 6 ++-
gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++
gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++++++++++++++++++++++
4 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index c2ec74b9d92..72f2f8f2753 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
+ {"zvfhmin", "f"},
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
@@ -216,6 +217,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
{"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+ {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2a16402265a..f34ca993689 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -200,9 +200,11 @@ enum riscv_entity
#define MASK_ZFHMIN (1 << 0)
#define MASK_ZFH (1 << 1)
+#define MASK_ZVFHMIN (1 << 2)
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
+#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 00000000000..8f8da1ecd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c
new file mode 100644
index 00000000000..285f64bd6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+#if defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
2023-05-25 12:46 [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option pan2.li
@ 2023-05-29 1:31 ` Li, Pan2
2023-05-29 2:17 ` Kito Cheng
2023-05-29 2:24 ` [PATCH v2] " pan2.li
1 sibling, 1 reply; 7+ messages in thread
From: Li, Pan2 @ 2023-05-29 1:31 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, Wang, Yanzhang
Sorry for disturbing but please help to take this PATCH in front of the reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.
Pan
-----Original Message-----
From: Li, Pan2 <pan2.li@intel.com>
Sent: Thursday, May 25, 2023 8:46 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
From: Pan Li <pan2.li@intel.com>
This patch would like to add new sub extension (aka ZVFHMIN) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFHMIN.
You can locate more information about ZVFHMIN from below spec doc.
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 3 ++
gcc/config/riscv/riscv-opts.h | 6 ++-
gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++
gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++++++++++++++++++++++
4 files changed, 63 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index c2ec74b9d92..72f2f8f2753 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
+ {"zvfhmin", "f"},
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
@@ -216,6 +217,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
{"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+ {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2a16402265a..f34ca993689 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -200,9 +200,11 @@ enum riscv_entity
#define MASK_ZFHMIN (1 << 0)
#define MASK_ZFH (1 << 1)
+#define MASK_ZVFHMIN (1 << 2)
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
+#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 00000000000..8f8da1ecd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32
+-mcmodel=medlow" } */ int foo() { }
diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c
new file mode 100644
index 00000000000..285f64bd6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow
+-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+#if defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
2023-05-29 1:31 ` Li, Pan2
@ 2023-05-29 2:17 ` Kito Cheng
2023-05-29 2:26 ` Li, Pan2
0 siblings, 1 reply; 7+ messages in thread
From: Kito Cheng @ 2023-05-29 2:17 UTC (permalink / raw)
To: Li, Pan2; +Cc: gcc-patches, juzhe.zhong, kito.cheng, Wang, Yanzhang
On Mon, May 29, 2023 at 9:32 AM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Sorry for disturbing but please help to take this PATCH in front of the reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2 <pan2.li@intel.com>
> Sent: Thursday, May 25, 2023 8:46 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFHMIN.
>
> You can locate more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
> ---
> gcc/common/config/riscv/riscv-common.cc | 3 ++
> gcc/config/riscv/riscv-opts.h | 6 ++-
> gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++
> gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++++++++++++++++++++++
> 4 files changed, 63 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..72f2f8f2753 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>
> {"zfh", "zfhmin"},
> {"zfhmin", "f"},
> + {"zvfhmin", "f"},
spec says: "The Zvfhmin extension depends on the Zve32f extension."
so this should be zve32f rather than f
> {"zhinx", "zhinxmin"},
> {"zhinxmin", "zfinx"},
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option
2023-05-25 12:46 [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option pan2.li
2023-05-29 1:31 ` Li, Pan2
@ 2023-05-29 2:24 ` pan2.li
2023-05-29 2:40 ` Kito Cheng
1 sibling, 1 reply; 7+ messages in thread
From: pan2.li @ 2023-05-29 2:24 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to add new sub extension (aka ZVFHMIN) to the
-march= option. To make it simple, only the sub extension itself is
involved in this patch, and the underlying FP16 related RVV intrinsic
API depends on the TARGET_ZVFHMIN.
The Zvfhmin extension depends on the Zve32f extension. You can locate
more information about ZVFHMIN from below spec doc.
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/common/config/riscv/riscv-common.cc | 3 ++
gcc/config/riscv/riscv-opts.h | 6 ++-
gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++
gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++++++++++++++++++++++
4 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index c2ec74b9d92..92edafb516d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
+ {"zvfhmin", "zve32f"},
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
@@ -216,6 +217,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
{"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+ {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2a16402265a..f34ca993689 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -200,9 +200,11 @@ enum riscv_entity
#define MASK_ZFHMIN (1 << 0)
#define MASK_ZFH (1 << 1)
+#define MASK_ZVFHMIN (1 << 2)
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
+#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 00000000000..8f8da1ecd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c
new file mode 100644
index 00000000000..285f64bd6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+#if defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
2023-05-29 2:17 ` Kito Cheng
@ 2023-05-29 2:26 ` Li, Pan2
0 siblings, 0 replies; 7+ messages in thread
From: Li, Pan2 @ 2023-05-29 2:26 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, kito.cheng, Wang, Yanzhang
Thanks Kito, update the PATCH v2 for addressing comments.
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619868.html
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Monday, May 29, 2023 10:18 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
On Mon, May 29, 2023 at 9:32 AM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> Sorry for disturbing but please help to take this PATCH in front of the reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2 <pan2.li@intel.com>
> Sent: Thursday, May 25, 2023 8:46 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2
> <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFHMIN.
>
> You can locate more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-
> vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
> ---
> gcc/common/config/riscv/riscv-common.cc | 3 ++
> gcc/config/riscv/riscv-opts.h | 6 ++-
> gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++
> gcc/testsuite/gcc.target/riscv/predef-26.c | 51
> ++++++++++++++++++++++
> 4 files changed, 63 insertions(+), 2 deletions(-) create mode 100644
> gcc/testsuite/gcc.target/riscv/arch-20.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..72f2f8f2753 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t
> riscv_implied_info[] =
>
> {"zfh", "zfhmin"},
> {"zfhmin", "f"},
> + {"zvfhmin", "f"},
spec says: "The Zvfhmin extension depends on the Zve32f extension."
so this should be zve32f rather than f
> {"zhinx", "zhinxmin"},
> {"zhinxmin", "zfinx"},
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option
2023-05-29 2:24 ` [PATCH v2] " pan2.li
@ 2023-05-29 2:40 ` Kito Cheng
2023-05-29 2:43 ` Li, Pan2
0 siblings, 1 reply; 7+ messages in thread
From: Kito Cheng @ 2023-05-29 2:40 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, kito.cheng, yanzhang.wang
LGTM
On Mon, May 29, 2023 at 10:24 AM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the
> -march= option. To make it simple, only the sub extension itself is
> involved in this patch, and the underlying FP16 related RVV intrinsic
> API depends on the TARGET_ZVFHMIN.
>
> The Zvfhmin extension depends on the Zve32f extension. You can locate
> more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/common/config/riscv/riscv-common.cc | 3 ++
> gcc/config/riscv/riscv-opts.h | 6 ++-
> gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++
> gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++++++++++++++++++++++
> 4 files changed, 63 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..92edafb516d 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>
> {"zfh", "zfhmin"},
> {"zfhmin", "f"},
> + {"zvfhmin", "zve32f"},
>
> {"zhinx", "zhinxmin"},
> {"zhinxmin", "zfinx"},
> @@ -216,6 +217,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>
> {"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>
> {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
> {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
> + {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>
> {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 2a16402265a..f34ca993689 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -200,9 +200,11 @@ enum riscv_entity
>
> #define MASK_ZFHMIN (1 << 0)
> #define MASK_ZFH (1 << 1)
> +#define MASK_ZVFHMIN (1 << 2)
>
> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> +#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
>
> #define MASK_ZMMUL (1 << 0)
> #define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c b/gcc/testsuite/gcc.target/riscv/arch-20.c
> new file mode 100644
> index 00000000000..8f8da1ecd65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 -mcmodel=medlow" } */
> +int foo()
> +{
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c
> new file mode 100644
> index 00000000000..285f64bd6c0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
> @@ -0,0 +1,51 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if defined(__riscv_c)
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_a)
> +#error "__riscv_a"
> +#endif
> +
> +#if defined(__riscv_zfh)
> +#error "__riscv_zfh"
> +#endif
> +
> +#if defined(__riscv_zfhmin)
> +#error "__riscv_zfhmin"
> +#endif
> +
> + return 0;
> +}
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option
2023-05-29 2:40 ` Kito Cheng
@ 2023-05-29 2:43 ` Li, Pan2
0 siblings, 0 replies; 7+ messages in thread
From: Li, Pan2 @ 2023-05-29 2:43 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, kito.cheng, Wang, Yanzhang
Committed, thanks Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Monday, May 29, 2023 10:40 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option
LGTM
On Mon, May 29, 2023 at 10:24 AM Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the
> -march= option. To make it simple, only the sub extension itself is
> involved in this patch, and the underlying FP16 related RVV intrinsic
> API depends on the TARGET_ZVFHMIN.
>
> The Zvfhmin extension depends on the Zve32f extension. You can locate
> more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-
> vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/common/config/riscv/riscv-common.cc | 3 ++
> gcc/config/riscv/riscv-opts.h | 6 ++-
> gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++
> gcc/testsuite/gcc.target/riscv/predef-26.c | 51
> ++++++++++++++++++++++
> 4 files changed, 63 insertions(+), 2 deletions(-) create mode 100644
> gcc/testsuite/gcc.target/riscv/arch-20.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..92edafb516d 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t
> riscv_implied_info[] =
>
> {"zfh", "zfhmin"},
> {"zfhmin", "f"},
> + {"zvfhmin", "zve32f"},
>
> {"zhinx", "zhinxmin"},
> {"zhinxmin", "zfinx"},
> @@ -216,6 +217,7 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
>
> {"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t
> riscv_ext_flag_table[] =
>
> {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
> {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
> + {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>
> {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h
> b/gcc/config/riscv/riscv-opts.h index 2a16402265a..f34ca993689 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -200,9 +200,11 @@ enum riscv_entity
>
> #define MASK_ZFHMIN (1 << 0)
> #define MASK_ZFH (1 << 1)
> +#define MASK_ZVFHMIN (1 << 2)
>
> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> +#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
>
> #define MASK_ZMMUL (1 << 0)
> #define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c
> b/gcc/testsuite/gcc.target/riscv/arch-20.c
> new file mode 100644
> index 00000000000..8f8da1ecd65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32
> +-mcmodel=medlow" } */ int foo() { }
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c
> b/gcc/testsuite/gcc.target/riscv/predef-26.c
> new file mode 100644
> index 00000000000..285f64bd6c0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
> @@ -0,0 +1,51 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow
> +-misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if defined(__riscv_c)
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_a)
> +#error "__riscv_a"
> +#endif
> +
> +#if defined(__riscv_zfh)
> +#error "__riscv_zfh"
> +#endif
> +
> +#if defined(__riscv_zfhmin)
> +#error "__riscv_zfhmin"
> +#endif
> +
> + return 0;
> +}
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-05-29 2:43 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-25 12:46 [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option pan2.li
2023-05-29 1:31 ` Li, Pan2
2023-05-29 2:17 ` Kito Cheng
2023-05-29 2:26 ` Li, Pan2
2023-05-29 2:24 ` [PATCH v2] " pan2.li
2023-05-29 2:40 ` Kito Cheng
2023-05-29 2:43 ` Li, Pan2
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