* [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE
@ 2023-10-09 13:37 Juzhe-Zhong
2023-10-09 13:48 ` Jeff Law
0 siblings, 1 reply; 3+ messages in thread
From: Juzhe-Zhong @ 2023-10-09 13:37 UTC (permalink / raw)
To: gcc-patches; +Cc: rguenther, jeffreyalaw, Juzhe-Zhong
Like ARM SVE, RVV is vectorizing these 2 cases in the same way.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-23.c: Add RVV like ARM SVE.
* gcc.dg/vect/slp-perm-10.c: Ditto.
---
gcc/testsuite/gcc.dg/vect/slp-23.c | 2 +-
gcc/testsuite/gcc.dg/vect/slp-perm-10.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-23.c b/gcc/testsuite/gcc.dg/vect/slp-23.c
index d32ee5ba73b..8836acf0330 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-23.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-23.c
@@ -114,5 +114,5 @@ int main (void)
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_perm } } } } */
/* SLP fails for the second loop with variable-length SVE because
the load size is greater than the minimum vector size. */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_perm xfail { aarch64_sve && vect_variable_length } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_perm xfail { { aarch64_sve || riscv_v } && vect_variable_length } } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-10.c b/gcc/testsuite/gcc.dg/vect/slp-perm-10.c
index 2cce30c2444..03de4c61b50 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-perm-10.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-perm-10.c
@@ -53,4 +53,4 @@ int main ()
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */
/* SLP fails for variable-length SVE because the load size is greater
than the minimum vector size. */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_perm xfail { aarch64_sve && vect_variable_length } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_perm xfail { { aarch64_sve || riscv_v } && vect_variable_length } } } } */
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE
2023-10-09 13:37 [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE Juzhe-Zhong
@ 2023-10-09 13:48 ` Jeff Law
2023-10-09 14:27 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Jeff Law @ 2023-10-09 13:48 UTC (permalink / raw)
To: Juzhe-Zhong, gcc-patches; +Cc: rguenther
On 10/9/23 07:37, Juzhe-Zhong wrote:
> Like ARM SVE, RVV is vectorizing these 2 cases in the same way.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/slp-23.c: Add RVV like ARM SVE.
> * gcc.dg/vect/slp-perm-10.c: Ditto.
OK
jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE
2023-10-09 13:48 ` Jeff Law
@ 2023-10-09 14:27 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-10-09 14:27 UTC (permalink / raw)
To: Jeff Law, Juzhe-Zhong, gcc-patches; +Cc: rguenther
Committed, thanks Jeff.
Pan
-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com>
Sent: Monday, October 9, 2023 9:49 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: rguenther@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE
On 10/9/23 07:37, Juzhe-Zhong wrote:
> Like ARM SVE, RVV is vectorizing these 2 cases in the same way.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/slp-23.c: Add RVV like ARM SVE.
> * gcc.dg/vect/slp-perm-10.c: Ditto.
OK
jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-10-09 13:37 [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE Juzhe-Zhong
2023-10-09 13:48 ` Jeff Law
2023-10-09 14:27 ` Li, Pan2
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