* [PATCH][committed] aarch64: Simplify sqmovun expander
@ 2023-05-10 11:04 Kyrylo Tkachov
0 siblings, 0 replies; only message in thread
From: Kyrylo Tkachov @ 2023-05-10 11:04 UTC (permalink / raw)
To: gcc-patches
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Hi all,
This patch is a no-op as it removes the explicit vec-concat-zero patterns in favour of vczle/vczbe.
This allows us to delete the explicit expander too. Tests are added to ensure the optimisation required
still triggers.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>_insn_le): Delete.
(aarch64_sqmovun<mode>_insn_be): Delete.
(aarch64_sqmovun<mode><vczle><vczbe>): New define_insn.
(aarch64_sqmovun<mode>): Delete expander.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/pr99195_4.c: Add tests for sqmovun.
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 363f64c7a25c563718e1f383b38c385c3daf0325..3698aab6d6df22ae780c0c6fb57ed222f14eff36 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5361,50 +5361,15 @@ (define_insn "aarch64_sqmovun<mode>"
[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
)
-(define_insn "aarch64_sqmovun<mode>_insn_le"
- [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
- (vec_concat:<VNARROWQ2>
- (unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w")]
- UNSPEC_SQXTUN)
- (match_operand:<VNARROWQ> 2 "aarch64_simd_or_scalar_imm_zero")))]
- "TARGET_SIMD && !BYTES_BIG_ENDIAN"
- "sqxtun\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
- [(set_attr "type" "neon_sat_shift_imm_narrow_q")]
-)
-
-(define_insn "aarch64_sqmovun<mode>_insn_be"
- [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
- (vec_concat:<VNARROWQ2>
- (match_operand:<VNARROWQ> 2 "aarch64_simd_or_scalar_imm_zero")
- (unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w")]
- UNSPEC_SQXTUN)))]
- "TARGET_SIMD && BYTES_BIG_ENDIAN"
+(define_insn "aarch64_sqmovun<mode><vczle><vczbe>"
+ [(set (match_operand:<VNARROWQ> 0 "register_operand" "=w")
+ (unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w")]
+ UNSPEC_SQXTUN))]
+ "TARGET_SIMD"
"sqxtun\\t%<vn2>0<Vmntype>, %<v>1<Vmtype>"
[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
)
-(define_expand "aarch64_sqmovun<mode>"
- [(set (match_operand:<VNARROWQ> 0 "register_operand")
- (unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand")]
- UNSPEC_SQXTUN))]
- "TARGET_SIMD"
- {
- rtx tmp = gen_reg_rtx (<VNARROWQ2>mode);
- if (BYTES_BIG_ENDIAN)
- emit_insn (gen_aarch64_sqmovun<mode>_insn_be (tmp, operands[1],
- CONST0_RTX (<VNARROWQ>mode)));
- else
- emit_insn (gen_aarch64_sqmovun<mode>_insn_le (tmp, operands[1],
- CONST0_RTX (<VNARROWQ>mode)));
-
- /* The intrinsic expects a narrow result, so emit a subreg that will get
- optimized away as appropriate. */
- emit_move_insn (operands[0], lowpart_subreg (<VNARROWQ>mode, tmp,
- <VNARROWQ2>mode));
- DONE;
- }
-)
-
(define_insn "aarch64_sqxtun2<mode>_le"
[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
(vec_concat:<VNARROWQ2>
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c
index 6127cb26781bbd2b727b3ac11489cf0a673e4597..8faf5691661eb55e304dcc564e8d8089a1f2f75c 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c
@@ -50,6 +50,14 @@ MYOP (uint32x4_t, uint64x2_t, uint32x2_t, OP, u64, u32) \
FUNC (movn)
FUNC (qmovn)
+#undef FUNC
+#define FUNC(OP) \
+MYOP (uint8x16_t, int16x8_t, uint8x8_t, OP, s16, u8) \
+MYOP (uint16x8_t, int32x4_t, uint16x4_t, OP, s32, u16) \
+MYOP (uint32x4_t, int64x2_t, uint32x2_t, OP, s64, u32) \
+
+FUNC (qmovun)
+
/* { dg-final { scan-assembler-not {\tfmov\t} } } */
/* { dg-final { scan-assembler-not {\tmov\t} } } */
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2023-05-10 11:04 [PATCH][committed] aarch64: Simplify sqmovun expander Kyrylo Tkachov
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