[PATCH][committed] aarch64: Add vect_concat with zeroes annotation to addp pattern

[PATCH][committed] aarch64: Add vect_concat with zeroes annotation to addp pattern

[Kyrylo Tkachov]

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Hi all,

Similar to others, the addp pattern can be safely annotated with <vczle><vczbe> to create
the implicit vec_concat-with-zero variants.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

	PR target/99195
	* config/aarch64/aarch64-simd.md (aarch64_addp<mode>): Rename to...
	(aarch64_addp<mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	PR target/99195
	* gcc.target/aarch64/simd/pr99195_1.c: Add testing for vpadd intrinsics.

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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a6449e4b93896d3f38122de5866b3fb4489bf632..263885828e50a8baa70a0927534e914ed47b18e4 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -7037,7 +7037,7 @@ (define_insn "aarch64_fac<optab><mode>"
 
 ;; addp
 
-(define_insn "aarch64_addp<mode>"
+(define_insn "aarch64_addp<mode><vczle><vczbe>"
   [(set (match_operand:VDQ_I 0 "register_operand" "=w")
         (unspec:VDQ_I
           [(match_operand:VDQ_I 1 "register_operand" "w")
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c
index b16191e3eaee8f4c679018708943caaafe75956c..562a7cd86926e9f9994ba357f546618fc22a05b0 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c
@@ -37,13 +37,18 @@ OPFOUR (T, IS, OS, S, OP2, OP3, OP4, OP5)
 FUNC (T, IS, OS, OP1, S)                \
 OPFIVE (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6)
 
-OPSIX (int8, 8, 16, s8, add, sub, mul, and, orr, eor)
-OPSIX (int16, 4, 8, s16, add, sub, mul, and, orr, eor)
-OPSIX (int32, 2, 4, s32, add, sub, mul, and, orr, eor)
+#define OPSEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7)        \
+FUNC (T, IS, OS, OP1, S)                \
+OPSIX (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6, OP7)
+
+
+OPSEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor)
+OPSEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor)
+OPSEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor)
 
-OPSIX (uint8, 8, 16, u8, add, sub, mul, and, orr, eor)
-OPSIX (uint16, 4, 8, u16, add, sub, mul, and, orr, eor)
-OPSIX (uint32, 2, 4, u32, add, sub, mul, and, orr, eor)
+OPSEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor)
+OPSEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor)
+OPSEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor)
 
 /* { dg-final { scan-assembler-not {\tfmov\td0, d0} } }  */
 /* { dg-final { scan-assembler-not {\tmov\tv0\.8b, v0\.8b} } }  */