* [PATCH][committed] aarch64: Add QI -> HI zero-extension for LDAPR
@ 2023-04-18 11:04 Kyrylo Tkachov
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From: Kyrylo Tkachov @ 2023-04-18 11:04 UTC (permalink / raw)
To: gcc-patches
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Hi all,
This patch is a straightforward extension of the zero-extending LDAPR pattern
to represent QI -> HI load-extends. This maps down to a LDAPRB-W instruction.
This lets us remove a redundant zero-extend in the new test function.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
* config/aarch64/atomics.md (*aarch64_atomic_load<ALLX:mode>_rcpc_zext):
Use SD_HSDI for destination mode iterator.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ldapr-zext.c: Add test for u8 to u16 extension.
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diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 5407cf7be49949c18577bc0e637bb06ccba1d49d..2a2e6814c56f2598046c50646b346cf22e5bc833 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -705,13 +705,13 @@ (define_insn "aarch64_atomic_load<mode>"
)
(define_insn "*aarch64_atomic_load<ALLX:mode>_rcpc_zext"
- [(set (match_operand:GPI 0 "register_operand" "=r")
- (zero_extend:GPI
+ [(set (match_operand:SD_HSDI 0 "register_operand" "=r")
+ (zero_extend:SD_HSDI
(unspec_volatile:ALLX
[(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q")
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPECV_LDAP)))]
- "TARGET_RCPC && (<GPI:sizen> > <ALLX:sizen>)"
+ "TARGET_RCPC && (<SD_HSDI:sizen> > <ALLX:sizen>)"
"ldapr<ALLX:atomic_sfx>\t%w0, %1"
)
diff --git a/gcc/testsuite/gcc.target/aarch64/ldapr-zext.c b/gcc/testsuite/gcc.target/aarch64/ldapr-zext.c
index 6f448eee1d9b109d08ca1dfa63d7156c6af95751..e9d90581e6707432f27ba917dc5025c087f195fd 100644
--- a/gcc/testsuite/gcc.target/aarch64/ldapr-zext.c
+++ b/gcc/testsuite/gcc.target/aarch64/ldapr-zext.c
@@ -65,3 +65,11 @@ TEST(u8_u32, u8, unsigned)
*/
TEST(u16_u32, u16, unsigned)
+/*
+**test_u8_u16:
+**...
+** ldaprb w0, \[x[0-9]+\]
+** ret
+*/
+TEST(u8_u16, u8, unsigned short)
+
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