* [PATCH][committed] aarch64: Factorise widening add/sub high-half expanders with iterators
@ 2023-04-19 14:43 Kyrylo Tkachov
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From: Kyrylo Tkachov @ 2023-04-19 14:43 UTC (permalink / raw)
To: gcc-patches
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Hi all,
I noticed these define_expand are almost identical modulo some string substitutions.
This patch compresses them together with a couple of code iterators.
No functional change intended.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_saddw2<mode>): Delete.
(aarch64_uaddw2<mode>): Delete.
(aarch64_ssubw2<mode>): Delete.
(aarch64_usubw2<mode>): Delete.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>): New define_expand.
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a38497f6e068e32258e9a770d41e2eabdb0607db..c88d68ab4a5bcf748d7c3669bdd84da7eed0157a 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4815,52 +4815,26 @@ (define_insn "aarch64_<ANY_EXTEND:su>addw2<mode>_internal"
[(set_attr "type" "neon_add_widen")]
)
-(define_expand "aarch64_saddw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand")
- (match_operand:<VWIDE> 1 "register_operand")
- (match_operand:VQW 2 "register_operand")]
- "TARGET_SIMD"
-{
- rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
- emit_insn (gen_aarch64_saddw2<mode>_internal (operands[0], operands[1],
- operands[2], p));
- DONE;
-})
-
-(define_expand "aarch64_uaddw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand")
- (match_operand:<VWIDE> 1 "register_operand")
- (match_operand:VQW 2 "register_operand")]
- "TARGET_SIMD"
-{
- rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
- emit_insn (gen_aarch64_uaddw2<mode>_internal (operands[0], operands[1],
- operands[2], p));
- DONE;
-})
-
-
-(define_expand "aarch64_ssubw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand")
- (match_operand:<VWIDE> 1 "register_operand")
- (match_operand:VQW 2 "register_operand")]
- "TARGET_SIMD"
-{
- rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
- emit_insn (gen_aarch64_ssubw2<mode>_internal (operands[0], operands[1],
- operands[2], p));
- DONE;
-})
-
-(define_expand "aarch64_usubw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand")
- (match_operand:<VWIDE> 1 "register_operand")
- (match_operand:VQW 2 "register_operand")]
- "TARGET_SIMD"
-{
- rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
- emit_insn (gen_aarch64_usubw2<mode>_internal (operands[0], operands[1],
- operands[2], p));
+(define_expand "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>"
+ [(set (match_operand:<VWIDE> 0 "register_operand")
+ (ADDSUB:<VWIDE>
+ (ANY_EXTEND:<VWIDE>
+ (vec_select:<VHALF>
+ (match_operand:VQW 2 "register_operand")
+ (match_dup 3)))
+ (match_operand:<VWIDE> 1 "register_operand")))]
+ "TARGET_SIMD"
+{
+ /* We still do an emit_insn rather than relying on the pattern above
+ because for the MINUS case the operands would need to be swapped
+ around. */
+ operands[3]
+ = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
+ emit_insn (gen_aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal(
+ operands[0],
+ operands[1],
+ operands[2],
+ operands[3]));
DONE;
})
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