* [PATCH][3/4][committed] aarch64: Convert UABAL and SABAL patterns to standard RTL codes
@ 2023-04-24 8:47 Kyrylo Tkachov
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From: Kyrylo Tkachov @ 2023-04-24 8:47 UTC (permalink / raw)
To: gcc-patches
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Hi all,
With the SABDL and UABDL patterns converted, the accumulating forms of them UABAL and SABAL are not much more complicated.
There's an accumulator argument that we, err, accumulate into with a PLUS once all the widening is done.
Some necessary renaming of patterns relating to the removal of UNSPEC_SABAL and UNSPEC_UABAL is included.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_<sur>abal<mode>): Rename to...
(aarch64_<su>abal<mode>): ... This. Use RTL codes instead of unspec.
(<sur>sadv16qi): Rename to...
(<su>sadv16qi): ... This. Adjust for the above.
* config/aarch64/aarch64-sve.md (<sur>sad<vsi2qi>): Rename to...
(<su>sad<vsi2qi>): ... This. Adjust for the above.
* config/aarch64/aarch64.md (UNSPEC_SABAL, UNSPEC_UABAL): Delete.
* config/aarch64/iterators.md (ABAL): Delete.
(sur): Remove handling of UNSPEC_SABAL and UNSPEC_UABAL.
[-- Attachment #2: abal.patch --]
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 2e087d4b400049c510f08759ea722f37fd8f9cb7..379c322fbd435b05024243096705de2b957f326e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -924,14 +924,20 @@ (define_expand "aarch64_<su>abdl2<mode>"
}
)
-(define_insn "aarch64_<sur>abal<mode>"
+(define_insn "aarch64_<su>abal<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
- (unspec:<VWIDE> [(match_operand:VD_BHSI 2 "register_operand" "w")
- (match_operand:VD_BHSI 3 "register_operand" "w")
- (match_operand:<VWIDE> 1 "register_operand" "0")]
- ABAL))]
+ (plus:<VWIDE>
+ (zero_extend:<VWIDE>
+ (minus:VD_BHSI
+ (USMAX:VD_BHSI
+ (match_operand:VD_BHSI 2 "register_operand" "w")
+ (match_operand:VD_BHSI 3 "register_operand" "w"))
+ (<max_opp>:VD_BHSI
+ (match_dup 2)
+ (match_dup 3))))
+ (match_operand:<VWIDE> 1 "register_operand" "0")))]
"TARGET_SIMD"
- "<sur>abal\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
+ "<su>abal\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "type" "neon_arith_acc<q>")]
)
@@ -976,10 +982,10 @@ (define_insn "aarch64_<sur>adalp<mode>"
;; but for TARGET_DOTPROD still emits a UDOT as the absolute difference is
;; unsigned.
-(define_expand "<sur>sadv16qi"
+(define_expand "<su>sadv16qi"
[(use (match_operand:V4SI 0 "register_operand"))
- (unspec:V16QI [(use (match_operand:V16QI 1 "register_operand"))
- (use (match_operand:V16QI 2 "register_operand"))] ABAL)
+ (USMAX:V16QI (match_operand:V16QI 1 "register_operand")
+ (match_operand:V16QI 2 "register_operand"))
(use (match_operand:V4SI 3 "register_operand"))]
"TARGET_SIMD"
{
@@ -987,18 +993,18 @@ (define_expand "<sur>sadv16qi"
{
rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode));
rtx abd = gen_reg_rtx (V16QImode);
- emit_insn (gen_aarch64_<sur>abdv16qi (abd, operands[1], operands[2]));
+ emit_insn (gen_aarch64_<su>abdv16qi (abd, operands[1], operands[2]));
emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3]));
DONE;
}
rtx reduc = gen_reg_rtx (V8HImode);
- emit_insn (gen_aarch64_<sur>abdl2v16qi (reduc, operands[1],
+ emit_insn (gen_aarch64_<su>abdl2v16qi (reduc, operands[1],
operands[2]));
- emit_insn (gen_aarch64_<sur>abalv8qi (reduc, reduc,
- gen_lowpart (V8QImode, operands[1]),
- gen_lowpart (V8QImode,
- operands[2])));
- emit_insn (gen_aarch64_<sur>adalpv8hi (operands[3], operands[3], reduc));
+ emit_insn (gen_aarch64_<su>abalv8qi (reduc, reduc,
+ gen_lowpart (V8QImode, operands[1]),
+ gen_lowpart (V8QImode,
+ operands[2])));
+ emit_insn (gen_aarch64_<su>adalpv8hi (operands[3], operands[3], reduc));
emit_move_insn (operands[0], operands[3]);
DONE;
}
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 7533b9566861a43e0d9edea8bcf4d8f177656dd5..b11b55f7ac718db199920b61bf3e4b4881c69660 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -6955,16 +6955,16 @@ (define_insn "@aarch64_<sur>dot_prod_lane<vsi2qi>"
;; [SU]ABD diff.b, p0/m, op1.b, op2.b
;; MOVPRFX op0, op3 // If necessary
;; UDOT op0.s, diff.b, ones.b
-(define_expand "<sur>sad<vsi2qi>"
+(define_expand "<su>sad<vsi2qi>"
[(use (match_operand:SVE_FULL_SDI 0 "register_operand"))
- (unspec:<VSI2QI> [(use (match_operand:<VSI2QI> 1 "register_operand"))
- (use (match_operand:<VSI2QI> 2 "register_operand"))] ABAL)
+ (USMAX:<VSI2QI> (match_operand:<VSI2QI> 1 "register_operand")
+ (match_operand:<VSI2QI> 2 "register_operand"))
(use (match_operand:SVE_FULL_SDI 3 "register_operand"))]
"TARGET_SVE"
{
rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
rtx diff = gen_reg_rtx (<VSI2QI>mode);
- emit_insn (gen_<sur>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
+ emit_insn (gen_<su>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
DONE;
}
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 7a622b73cb2765066fb56a10b1db2c2c11cf62a1..575aaf82eaf0a118a51a2e067f991a87401f5b9f 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -204,7 +204,6 @@ (define_c_enum "unspec" [
UNSPEC_PRLG_STK
UNSPEC_REV
UNSPEC_RBIT
- UNSPEC_SABAL
UNSPEC_SABAL2
UNSPEC_SADALP
UNSPEC_SCVTF
@@ -226,7 +225,6 @@ (define_c_enum "unspec" [
UNSPEC_TLSLE24
UNSPEC_TLSLE32
UNSPEC_TLSLE48
- UNSPEC_UABAL
UNSPEC_UABAL2
UNSPEC_UADALP
UNSPEC_UCVTF
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 5818ea15f7d31be2f180da4c247c27647f84f25e..cc471ae90d157d7356a0ad4c1ac591aa6227c555 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2562,9 +2562,6 @@ (define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec")
;; Int Iterators.
;; -------------------------------------------------------------------
-;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
-(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
-
;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions.
(define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2])
@@ -3349,7 +3346,6 @@ (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
(UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
(UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
(UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
- (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
(UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u")
(UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
(UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
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