From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"Liu, Hongtao" <hongtao.liu@intel.com>
Subject: RE: [PATCH] i386: Extend cvtps2pd to memory
Date: Thu, 30 Jun 2022 07:24:38 +0000 [thread overview]
Message-ID: <SA1PR11MB59461984EB152117C1B267C2ECBA9@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CAFULd4aJ_a+zQh_L5eeAiBpiGAY8gcLuK9psQ6fXftc4k-TJig@mail.gmail.com>
> -----Original Message-----
> From: Uros Bizjak <ubizjak@gmail.com>
> Sent: Thursday, June 30, 2022 2:20 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao <hongtao.liu@intel.com>
> Subject: Re: [PATCH] i386: Extend cvtps2pd to memory
>
> On Thu, Jun 30, 2022 at 7:59 AM Haochen Jiang <haochen.jiang@intel.com>
> wrote:
> >
> > Hi all,
> >
> > This patch aims to fix the cvtps2pd insn, which should also work on
> > memory operand but currently does not. After this fix, when loop == 2,
> > it will eliminate movq instruction.
> >
> > Regtested on x86_64-pc-linux-gnu. Ok for trunk?
> >
> > BRs,
> > Haochen
> >
> > gcc/ChangeLog:
> >
> > PR target/43618
> > * config/i386/sse.md (extendv2sfv2df2): New define_expand.
> > (sse2_cvtps2pd_load<mask_name>): Rename extendvsdfv2df2.
> >
> > gcc/testsuite/ChangeLog:
> >
> > PR target/43618
> > * gcc.target/i386/pr43618-1.c: New test.
>
> This patch could be as simple as:
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index
> 8cd0f617bf3..c331445cb2d 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -9195,7 +9195,7 @@
> (define_insn "extendv2sfv2df2"
> [(set (match_operand:V2DF 0 "register_operand" "=v")
> (float_extend:V2DF
> - (match_operand:V2SF 1 "register_operand" "v")))]
> + (match_operand:V2SF 1 "nonimmediate_operand" "vm")))]
> "TARGET_MMX_WITH_SSE"
> "%vcvtps2pd\t{%1, %0|%0, %1}"
> [(set_attr "type" "ssecvt")
We also tested on this version, it is ok.
The reason why the patch looks like this is because in the previous insn
sse2_cvtps2pd<mask_name>, the constraint vm and vector_operand
actually does not match the actual instruction. Memory operand is V2SF,
not V4SF.
Therefore, we changed the constraint in that insn. Then it caused another issue.
For memory operand, it seems that we cannot generate those mask instructions.
So I change the pattern to how extendv2hfv2df2 works.
Haochen
> Uros.
next prev parent reply other threads:[~2022-06-30 7:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-30 5:59 Haochen Jiang
2022-06-30 6:20 ` Uros Bizjak
2022-06-30 7:24 ` Jiang, Haochen [this message]
2022-06-30 7:41 ` Uros Bizjak
2022-06-30 8:45 ` Uros Bizjak
2022-06-30 8:53 ` Uros Bizjak
2022-06-30 8:57 ` Liu, Hongtao
2022-07-04 5:09 ` Jiang, Haochen
2022-07-04 6:17 ` Uros Bizjak
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