Re: [PATCH][X86_64] Separate znver4 insn reservations from older znvers

[Alexander Monakov <amonakov@ispras.ru>]

On Mon, 14 Nov 2022, Joshi, Tejas Sanjay wrote:

> [Public]
> 
> Hi,

Hi. I'm still waiting for feedback on fixes for existing models:
https://inbox.sourceware.org/gcc-patches/5ae6fc21-edc6-133-aee2-a41e16eb5b7@ispras.ru/T/#t
did you have a chance to look at those?

> PFA the patch which adds znver4 instruction reservations separately from older
> znver versions:
> * This also models separate div, fdiv and ssediv units accordingly.

Why are you modeling 'fdiv' and 'ssediv' separately? When preparing the above
patches, I checked that x87 and SSE divisions use the same hardware unit, and
I don't see a strong reason to artificially clone it in the model.

(integer divider is a separate unit from the floating-point divider)

> * Does not blow-up the insn-automata.cc size (it grew from 201502 to 206141 for me.)
> * The patch successfully builds, bootstraps, and passes make check.
> * I have also run spec, showing no regressions for 1-copy 3-iteration runs. However, I observe 1.5% gain for 507.cactuBSSN_r.

I have a question on AVX512 modeling in your patch:

> +;; AVX instructions
> +(define_insn_reservation "znver4_sse_log" 1
> +			 (and (eq_attr "cpu" "znver4")
> +			      (and (eq_attr "type" "sselog,sselog1")
> +				   (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF")
> +				    (eq_attr "memory" "none"))))
> +			 "znver4-direct,znver4-fpu")
> +
> +(define_insn_reservation "znver4_sse_log_evex" 1
> +			 (and (eq_attr "cpu" "znver4")
> +			      (and (eq_attr "type" "sselog,sselog1")
> +				   (and (eq_attr "mode" "V16SF,V8DF")
> +				    (eq_attr "memory" "none"))))
> +			 "znver4-direct,znver4-fpu0+znver4-fpu1|znver4-fpu2+znver4-fpu3")
> +

This is an AVX512 instruction, and you're modeling that it occupies two ports at
once and thus has half throughput, but later in the AVX512 section:

> +;; AVX512 instructions
> +(define_insn_reservation "znver4_sse_mul_evex" 3
> +			 (and (eq_attr "cpu" "znver4")
> +			      (and (eq_attr "type" "ssemul")
> +				   (and (eq_attr "mode" "V16SF,V8DF")
> +				    (eq_attr "memory" "none"))))
> +			 "znver4-double,znver4-fpu0|znver4-fpu3")

none of the instructions are modeled this way. If that's on purpose, can you
add a comment? It's surprising, since generally AVX512 has half throughput
compared to AVX256 on Zen 4, but the model doesn't seem to reflect that.

Alexander