[PATCH 1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations.

[PATCH 1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations.

[Lulu Cheng]

There are two mode iterators defined in the loongarch.md:
	(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
  and
	(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
Replace the mode in the bit arithmetic from GPR to X.

Since the bitwise operation instruction does not distinguish between 64-bit,
32-bit, etc., it is necessary to perform symbolic expansion if the bitwise
operation is less than 64 bits.
The original definition would have generated a lot of redundant symbolic
extension instructions. This problem is optimized with reference to the
implementation of RISCV.

Add this patch spec2017 500.perlbench performance improvement by 1.8%

gcc/ChangeLog:

	* config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
	(*nor<mode>3): Likewise.
	(nor<mode>3): Likewise.
	(*negsi2_extended): New template.
	(*<optab>si3_internal): Likewise.
	(*one_cmplsi2_internal): Likewise.
	(*norsi3_internal): Likewise.
	(*<optab>nsi_internal): Likewise.
	(bytepick_w_<bytepick_imm>_extend): Modify this template according to the
	modified bit operation to make the optimization work.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/sign-extend-bitwise.c: New test.
---
 gcc/config/loongarch/loongarch.md             | 93 ++++++++++++++-----
 .../loongarch/sign-extend-bitwise.c           | 21 +++++
 2 files changed, 90 insertions(+), 24 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d1f5b94f5d6..436b9a93235 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -736,7 +736,7 @@ (define_insn "sub<mode>3"
 
 (define_insn "sub<mode>3"
   [(set (match_operand:GPR 0 "register_operand" "=r")
-	(minus:GPR (match_operand:GPR 1 "register_operand" "rJ")
+	(minus:GPR (match_operand:GPR 1 "register_operand" "r")
 		   (match_operand:GPR 2 "register_operand" "r")))]
   ""
   "sub.<d>\t%0,%z1,%2"
@@ -1412,13 +1412,13 @@ (define_insn "neg<mode>2"
   [(set_attr "alu_type"	"sub")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "one_cmpl<mode>2"
-  [(set (match_operand:GPR 0 "register_operand" "=r")
-	(not:GPR (match_operand:GPR 1 "register_operand" "r")))]
-  ""
-  "nor\t%0,%.,%1"
-  [(set_attr "alu_type" "not")
-   (set_attr "mode" "<MODE>")])
+(define_insn "*negsi2_extended"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))]
+  "TARGET_64BIT"
+  "sub.w\t%0,%.,%1"
+  [(set_attr "alu_type" "sub")
+   (set_attr "mode" "SI")])
 
 (define_insn "neg<mode>2"
   [(set (match_operand:ANYF 0 "register_operand" "=f")
@@ -1438,14 +1438,39 @@ (define_insn "neg<mode>2"
 ;;
 
 (define_insn "<optab><mode>3"
-  [(set (match_operand:GPR 0 "register_operand" "=r,r")
-	(any_bitwise:GPR (match_operand:GPR 1 "register_operand" "%r,r")
-			 (match_operand:GPR 2 "uns_arith_operand" "r,K")))]
+  [(set (match_operand:X 0 "register_operand" "=r,r")
+	(any_bitwise:X (match_operand:X 1 "register_operand" "%r,r")
+		       (match_operand:X 2 "uns_arith_operand" "r,K")))]
   ""
   "<insn>%i2\t%0,%1,%2"
   [(set_attr "type" "logical")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*<optab>si3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r")
+			(match_operand:SI 2 "uns_arith_operand"    " r,K")))]
+  "TARGET_64BIT"
+  "<insn>%i2\t%0,%1,%2"
+  [(set_attr "type" "logical")
+   (set_attr "mode" "SI")])
+
+(define_insn "one_cmpl<mode>2"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(not:X (match_operand:X 1 "register_operand" "r")))]
+  ""
+  "nor\t%0,%.,%1"
+  [(set_attr "alu_type" "not")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "*one_cmplsi2_internal"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operand:SI 1 "register_operand" " r")))]
+  "TARGET_64BIT"
+  "nor\t%0,%.,%1"
+  [(set_attr "type" "logical")
+   (set_attr "mode" "SI")])
+
 (define_insn "and<mode>3_extended"
   [(set (match_operand:GPR 0 "register_operand" "=r")
 	(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "r")
@@ -1561,25 +1586,43 @@ (define_insn "*iorhi3"
   [(set_attr "type" "logical")
    (set_attr "mode" "HI")])
 
-(define_insn "*nor<mode>3"
-  [(set (match_operand:GPR 0 "register_operand" "=r")
-	(and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "%r"))
-		 (not:GPR (match_operand:GPR 2 "register_operand" "r"))))]
+(define_insn "nor<mode>3"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(and:X (not:X (match_operand:X 1 "register_operand" "%r"))
+		 (not:X (match_operand:X 2 "register_operand" "r"))))]
   ""
   "nor\t%0,%1,%2"
   [(set_attr "type" "logical")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*norsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(and:SI (not:SI (match_operand:SI 1 "register_operand" "%r"))
+		 (not:SI (match_operand:SI 2 "register_operand" "r"))))]
+  "TARGET_64BIT"
+  "nor\t%0,%1,%2"
+  [(set_attr "type" "logical")
+   (set_attr "mode" "SI")])
+
 (define_insn "<optab>n<mode>"
-  [(set (match_operand:GPR 0 "register_operand" "=r")
-	(neg_bitwise:GPR
-	    (not:GPR (match_operand:GPR 1 "register_operand" "r"))
-	    (match_operand:GPR 2 "register_operand" "r")))]
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(neg_bitwise:X
+	    (not:X (match_operand:X 1 "register_operand" "r"))
+	    (match_operand:X 2 "register_operand" "r")))]
   ""
   "<insn>n\t%0,%2,%1"
   [(set_attr "type" "logical")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*<optab>nsi_internal"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg_bitwise:SI
+	    (not:SI (match_operand:SI 1 "register_operand" "r"))
+	    (match_operand:SI 2 "register_operand" "r")))]
+  "TARGET_64BIT"
+  "<insn>n\t%0,%2,%1"
+  [(set_attr "type" "logical")
+   (set_attr "mode" "SI")])
 \f
 ;;
 ;;  ....................
@@ -3167,7 +3210,6 @@ (define_expand "condjump"
 		      (label_ref (match_operand 1))
 		      (pc)))])
 
-
 \f
 ;;
 ;;  ....................
@@ -3967,10 +4009,13 @@ (define_insn "bytepick_w_<bytepick_imm>"
 (define_insn "bytepick_w_<bytepick_imm>_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI
-	  (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
-			    (const_int <bytepick_w_lshiftrt_amount>))
-		  (ashift (match_operand:SI 2 "register_operand" "r")
-			  (const_int bytepick_w_ashift_amount)))))]
+	 (subreg:SI
+	  (ior:DI (subreg:DI (lshiftrt
+			      (match_operand:SI 1 "register_operand" "r")
+			      (const_int <bytepick_w_lshiftrt_amount>)) 0)
+		  (subreg:DI (ashift
+			      (match_operand:SI 2 "register_operand" "r")
+			      (const_int bytepick_w_ashift_amount)) 0)) 0)))]
   "TARGET_64BIT"
   "bytepick.w\t%0,%1,%2,<bytepick_imm>"
   [(set_attr "mode" "SI")])
diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
new file mode 100644
index 00000000000..5753ef69db2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=lp64d -O2" } */
+/* { dg-final { scan-assembler-not "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" } } */
+
+struct pmop
+{
+  unsigned int op_pmflags;
+  unsigned int op_pmpermflags;
+};
+unsigned int PL_hints;
+
+struct pmop *pmop;
+void
+Perl_newPMOP (int type, int flags)
+{
+  if (PL_hints & 0x00100000)
+    pmop->op_pmpermflags |= 0x0001;
+  if (PL_hints & 0x00000004)
+    pmop->op_pmpermflags |= 0x0800;
+  pmop->op_pmflags = pmop->op_pmpermflags;
+}
-- 
2.39.3

[PATCH 2/3] LoongArch: Redundant sign extension elimination optimization.

[Lulu Cheng]

From: liwei <liwei@loongson.cn>

We found that the current combine optimization pass in gcc cannot handle
the following redundant sign extension situations:

(insn 77 76 78 5 (set (reg:SI 143)
	(plus:SI (subreg/s/u:SI (reg/v:DI 104 [ len ]) 0)
	    (const_int 1 [0x1]))) {addsi3}
    (expr_list:REG_DEAD (reg/v:DI 104 [ len ])
	(nil)))
(insn 78 77 82 5 (set (reg/v:DI 104 [ len ])
	(sign_extend:DI (reg:SI 143))) {extendsidi2}
	(nil))

Because reg:SI 143 is not died or set in insn 78, no replacement merge will
be performed for the insn sequence. We adjusted the add template to eliminate
redundant sign extensions during the expand pass.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (add<mode>3): Removed.
	(*addsi3): New.
	(addsi3): New.
	(adddi3): New.
	(*addsi3_extended): Removed.
	(addsi3_extended): New.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/sign-extend.c: Moved to...
	* gcc.target/loongarch/sign-extend-1.c: ...here.
	* gcc.target/loongarch/sign-extend-2.c: New test.
---
 gcc/config/loongarch/loongarch.md             | 93 ++++++++++++++++---
 .../{sign-extend.c => sign-extend-1.c}        |  0
 .../gcc.target/loongarch/sign-extend-2.c      | 59 ++++++++++++
 3 files changed, 137 insertions(+), 15 deletions(-)
 rename gcc/testsuite/gcc.target/loongarch/{sign-extend.c => sign-extend-1.c} (100%)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-2.c

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 436b9a93235..17ec401f535 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -657,15 +657,15 @@ (define_insn "add<mode>3"
   [(set_attr "type" "fadd")
    (set_attr "mode" "<UNITMODE>")])
 
-(define_insn_and_split "add<mode>3"
-  [(set (match_operand:GPR 0 "register_operand" "=r,r,r,r,r,r,r")
-	(plus:GPR (match_operand:GPR 1 "register_operand" "r,r,r,r,r,r,r")
-		  (match_operand:GPR 2 "plus_<mode>_operand"
+(define_insn_and_split "*addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
+	(plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r,r,r")
+		  (match_operand:SI 2 "plus_si_operand"
 				       "r,I,La,Lb,Lc,Ld,Le")))]
   ""
   "@
-   add.<d>\t%0,%1,%2
-   addi.<d>\t%0,%1,%2
+   add.w\t%0,%1,%2
+   addi.w\t%0,%1,%2
    #
    * operands[2] = GEN_INT (INTVAL (operands[2]) / 65536); \
      return \"addu16i.d\t%0,%1,%2\";
@@ -674,25 +674,88 @@ (define_insn_and_split "add<mode>3"
    #"
   "CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \
    && !ADDU16I_OPERAND (INTVAL (operands[2]))"
-  [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
+  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
+   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
   {
-    loongarch_split_plus_constant (&operands[2], <MODE>mode);
+    loongarch_split_plus_constant (&operands[2], SImode);
   }
   [(set_attr "alu_type" "add")
-   (set_attr "mode" "<MODE>")
+   (set_attr "mode" "SI")
    (set_attr "insn_count" "1,1,2,1,2,2,2")
    (set (attr "enabled")
       (cond
-	[(match_test "<MODE>mode != DImode && which_alternative == 4")
+	[(match_test "which_alternative == 4")
 	 (const_string "no")
-	 (match_test "<MODE>mode != DImode && which_alternative == 5")
-	 (const_string "no")
-	 (match_test "<MODE>mode != SImode && which_alternative == 6")
+	 (match_test "which_alternative == 5")
+	 (const_string "no")]
+	(const_string "yes")))])
+
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
+	(plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r")
+		 (match_operand:SI 2 "plus_si_operand"  "r,I,La,Le,Lb")))]
+  ""
+{
+  if (TARGET_64BIT)
+    {
+      if (CONST_INT_P (operands[2]) && !IMM12_INT (operands[2])
+	  && ADDU16I_OPERAND (INTVAL (operands[2])))
+	{
+	  rtx t1 = gen_reg_rtx (DImode);
+	  rtx t2 = gen_reg_rtx (DImode);
+	  rtx t3 = gen_reg_rtx (DImode);
+	  emit_insn (gen_extend_insn (t1, operands[1], DImode, SImode, 0));
+	  t2 = operands[2];
+	  emit_insn (gen_adddi3 (t3, t1, t2));
+	  t3 = gen_lowpart (SImode, t3);
+	  emit_move_insn (operands[0], t3);
+	  DONE;
+	}
+      else
+	{
+	  rtx t = gen_reg_rtx (DImode);
+	  emit_insn (gen_addsi3_extended (t, operands[1], operands[2]));
+	  t = gen_lowpart (SImode, t);
+	  SUBREG_PROMOTED_VAR_P (t) = 1;
+	  SUBREG_PROMOTED_SET (t, SRP_SIGNED);
+	  emit_move_insn (operands[0], t);
+	  DONE;
+	}
+    }
+})
+
+(define_insn_and_split "adddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r")
+	(plus:DI (match_operand:DI 1 "register_operand" "r,r,r,r,r,r,r")
+		  (match_operand:DI 2 "plus_di_operand"
+				       "r,I,La,Lb,Lc,Ld,Le")))]
+  ""
+  "@
+   add.d\t%0,%1,%2
+   addi.d\t%0,%1,%2
+   #
+   * operands[2] = GEN_INT (INTVAL (operands[2]) / 65536); \
+     return \"addu16i.d\t%0,%1,%2\";
+   #
+   #
+   #"
+  "CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \
+   && !ADDU16I_OPERAND (INTVAL (operands[2]))"
+  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
+   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
+  {
+    loongarch_split_plus_constant (&operands[2], DImode);
+  }
+  [(set_attr "alu_type" "add")
+   (set_attr "mode" "DI")
+   (set_attr "insn_count" "1,1,2,1,2,2,2")
+   (set (attr "enabled")
+      (cond
+	[(match_test "which_alternative == 6")
 	 (const_string "no")]
 	(const_string "yes")))])
 
-(define_insn_and_split "*addsi3_extended"
+(define_insn_and_split "addsi3_extended"
   [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
 	(sign_extend:DI
 	     (plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/loongarch/sign-extend.c
rename to gcc/testsuite/gcc.target/loongarch/sign-extend-1.c
diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
new file mode 100644
index 00000000000..a45dde4f73f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=lp64d -O2" } */
+/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */
+
+#include <stdint.h>
+#define my_min(x, y) ((x) < (y) ? (x) : (y))
+
+void
+bt_skip_func (const uint32_t len_limit, const uint32_t pos,
+              const uint8_t *const cur, uint32_t cur_match,
+              uint32_t *const son, const uint32_t cyclic_pos,
+              const uint32_t cyclic_size)
+{
+  uint32_t *ptr0 = son + (cyclic_pos << 1) + 1;
+  uint32_t *ptr1 = son + (cyclic_pos << 1);
+
+  uint32_t len0 = 0;
+  uint32_t len1 = 0;
+
+  while (1)
+    {
+      const uint32_t delta = pos - cur_match;
+      uint32_t *pair
+          = son
+            + ((cyclic_pos - delta + (delta > cyclic_pos ? cyclic_size : 0))
+               << 1);
+      const uint8_t *pb = cur - delta;
+      uint32_t len = my_min (len0, len1);
+
+      if (pb[len] == cur[len])
+        {
+          while (++len != len_limit)
+            if (pb[len] != cur[len])
+              break;
+
+          if (len == len_limit)
+            {
+              *ptr1 = pair[0];
+              *ptr0 = pair[1];
+              return;
+            }
+        }
+
+      if (pb[len] < cur[len])
+        {
+          *ptr1 = cur_match;
+          ptr1 = pair + 1;
+          cur_match = *ptr1;
+          len1 = len;
+        }
+      else
+        {
+          *ptr0 = cur_match;
+          ptr0 = pair;
+          cur_match = *ptr0;
+          len0 = len;
+        }
+    }
+}
-- 
2.39.3

[PATCH 3/3] LoongArch: Redundant sign extension elimination optimization 2.

[Lulu Cheng]

From: liwei <liwei@loongson.cn>

Eliminate the redundant sign extension that exists after the conditional
move when the target register is SImode.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
	Adjust.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/sign-extend-2.c: Adjust.
---
 gcc/config/loongarch/loongarch.cc                  | 2 ++
 gcc/testsuite/gcc.target/loongarch/sign-extend-2.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index ec376a7228a..4b757b30b64 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -5371,6 +5371,8 @@ loongarch_expand_conditional_move (rtx *operands)
 	  rtx temp3 = gen_reg_rtx (mode);
 	  emit_insn (gen_rtx_SET (temp3, gen_rtx_IOR (mode, temp, temp2)));
 	  temp3 = gen_lowpart (GET_MODE (operands[0]), temp3);
+	  SUBREG_PROMOTED_VAR_P (temp3) = 1;
+	  SUBREG_PROMOTED_SET (temp3, SRP_SIGNED);
 	  loongarch_emit_move (operands[0], temp3);
 	}
       else
diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
index a45dde4f73f..428535cb8e3 100644
--- a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-mabi=lp64d -O2" } */
-/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */
+/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 0 } } */
 
 #include <stdint.h>
 #define my_min(x, y) ((x) < (y) ? (x) : (y))
-- 
2.39.3

Re: [PATCH 2/3] LoongArch: Redundant sign extension elimination optimization.

[Xi Ruoyao]

On Sat, 2024-01-06 at 16:54 +0800, Lulu Cheng wrote:
> +(define_expand "addsi3"
> +  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
> +	(plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r")
> +		 (match_operand:SI 2 "plus_si_operand"  "r,I,La,Le,Lb")))]
> +  ""
> +{
> +  if (TARGET_64BIT)

I think for 32 bit we can just skip the expand and use *addsi3?  I. e.
add TARGET_64BIT into the expand condition two lines above.

> +    {
> +      if (CONST_INT_P (operands[2]) && !IMM12_INT (operands[2])
> +	  && ADDU16I_OPERAND (INTVAL (operands[2])))
> +	{
> +	  rtx t1 = gen_reg_rtx (DImode);
> +	  rtx t2 = gen_reg_rtx (DImode);
> +	  rtx t3 = gen_reg_rtx (DImode);
> +	  emit_insn (gen_extend_insn (t1, operands[1], DImode, SImode, 0));
> +	  t2 = operands[2];
> +	  emit_insn (gen_adddi3 (t3, t1, t2));
> +	  t3 = gen_lowpart (SImode, t3);
> +	  emit_move_insn (operands[0], t3);
> +	  DONE;
> +	}
> +      else
> +	{
> +	  rtx t = gen_reg_rtx (DImode);
> +	  emit_insn (gen_addsi3_extended (t, operands[1], operands[2]));

AFAIK if !TARGET_64BIT a DImode should be actually a pair of hardware
registers, but addsi3_extended don't output such a pair so this seems
invalid...

> +	  t = gen_lowpart (SImode, t);
> +	  SUBREG_PROMOTED_VAR_P (t) = 1;
> +	  SUBREG_PROMOTED_SET (t, SRP_SIGNED);
> +	  emit_move_insn (operands[0], t);
> +	  DONE;
> +	}
> +    }
> +})

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Re: [PATCH 1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations.

[Xi Ruoyao]

On Sat, 2024-01-06 at 16:54 +0800, Lulu Cheng wrote:
> There are two mode iterators defined in the loongarch.md:
> 	(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
>   and
> 	(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
> Replace the mode in the bit arithmetic from GPR to X.
> 
> Since the bitwise operation instruction does not distinguish between 64-bit,
> 32-bit, etc., it is necessary to perform symbolic expansion if the bitwise
> operation is less than 64 bits.
> The original definition would have generated a lot of redundant symbolic
> extension instructions. This problem is optimized with reference to the
> implementation of RISCV.
> 
> Add this patch spec2017 500.perlbench performance improvement by 1.8%
> 
> gcc/ChangeLog:
> 
> 	* config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
> 	(*nor<mode>3): Likewise.
> 	(nor<mode>3): Likewise.
> 	(*negsi2_extended): New template.
> 	(*<optab>si3_internal): Likewise.
> 	(*one_cmplsi2_internal): Likewise.
> 	(*norsi3_internal): Likewise.
> 	(*<optab>nsi_internal): Likewise.
> 	(bytepick_w_<bytepick_imm>_extend): Modify this template according to the
> 	modified bit operation to make the optimization work.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/loongarch/sign-extend-bitwise.c: New test.
> ---

LGTM.

>  gcc/config/loongarch/loongarch.md             | 93 ++++++++++++++-----
>  .../loongarch/sign-extend-bitwise.c           | 21 +++++
>  2 files changed, 90 insertions(+), 24 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
> 
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index d1f5b94f5d6..436b9a93235 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -736,7 +736,7 @@ (define_insn "sub<mode>3"
>  
>  (define_insn "sub<mode>3"
>    [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(minus:GPR (match_operand:GPR 1 "register_operand" "rJ")
> +	(minus:GPR (match_operand:GPR 1 "register_operand" "r")
>  		   (match_operand:GPR 2 "register_operand" "r")))]
>    ""
>    "sub.<d>\t%0,%z1,%2"
> @@ -1412,13 +1412,13 @@ (define_insn "neg<mode>2"
>    [(set_attr "alu_type"	"sub")
>     (set_attr "mode" "<MODE>")])
>  
> -(define_insn "one_cmpl<mode>2"
> -  [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(not:GPR (match_operand:GPR 1 "register_operand" "r")))]
> -  ""
> -  "nor\t%0,%.,%1"
> -  [(set_attr "alu_type" "not")
> -   (set_attr "mode" "<MODE>")])
> +(define_insn "*negsi2_extended"
> +  [(set (match_operand:DI 0 "register_operand" "=r")
> +	(sign_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))]
> +  "TARGET_64BIT"
> +  "sub.w\t%0,%.,%1"
> +  [(set_attr "alu_type" "sub")
> +   (set_attr "mode" "SI")])
>  
>  (define_insn "neg<mode>2"
>    [(set (match_operand:ANYF 0 "register_operand" "=f")
> @@ -1438,14 +1438,39 @@ (define_insn "neg<mode>2"
>  ;;
>  
>  (define_insn "<optab><mode>3"
> -  [(set (match_operand:GPR 0 "register_operand" "=r,r")
> -	(any_bitwise:GPR (match_operand:GPR 1 "register_operand" "%r,r")
> -			 (match_operand:GPR 2 "uns_arith_operand" "r,K")))]
> +  [(set (match_operand:X 0 "register_operand" "=r,r")
> +	(any_bitwise:X (match_operand:X 1 "register_operand" "%r,r")
> +		       (match_operand:X 2 "uns_arith_operand" "r,K")))]
>    ""
>    "<insn>%i2\t%0,%1,%2"
>    [(set_attr "type" "logical")
>     (set_attr "mode" "<MODE>")])
>  
> +(define_insn "*<optab>si3_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r,r")
> +	(any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r")
> +			(match_operand:SI 2 "uns_arith_operand"    " r,K")))]
> +  "TARGET_64BIT"
> +  "<insn>%i2\t%0,%1,%2"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
> +
> +(define_insn "one_cmpl<mode>2"
> +  [(set (match_operand:X 0 "register_operand" "=r")
> +	(not:X (match_operand:X 1 "register_operand" "r")))]
> +  ""
> +  "nor\t%0,%.,%1"
> +  [(set_attr "alu_type" "not")
> +   (set_attr "mode" "<MODE>")])
> +
> +(define_insn "*one_cmplsi2_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(not:SI (match_operand:SI 1 "register_operand" " r")))]
> +  "TARGET_64BIT"
> +  "nor\t%0,%.,%1"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
> +
>  (define_insn "and<mode>3_extended"
>    [(set (match_operand:GPR 0 "register_operand" "=r")
>  	(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "r")
> @@ -1561,25 +1586,43 @@ (define_insn "*iorhi3"
>    [(set_attr "type" "logical")
>     (set_attr "mode" "HI")])
>  
> -(define_insn "*nor<mode>3"
> -  [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "%r"))
> -		 (not:GPR (match_operand:GPR 2 "register_operand" "r"))))]
> +(define_insn "nor<mode>3"
> +  [(set (match_operand:X 0 "register_operand" "=r")
> +	(and:X (not:X (match_operand:X 1 "register_operand" "%r"))
> +		 (not:X (match_operand:X 2 "register_operand" "r"))))]
>    ""
>    "nor\t%0,%1,%2"
>    [(set_attr "type" "logical")
>     (set_attr "mode" "<MODE>")])
>  
> +(define_insn "*norsi3_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(and:SI (not:SI (match_operand:SI 1 "register_operand" "%r"))
> +		 (not:SI (match_operand:SI 2 "register_operand" "r"))))]
> +  "TARGET_64BIT"
> +  "nor\t%0,%1,%2"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
> +
>  (define_insn "<optab>n<mode>"
> -  [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(neg_bitwise:GPR
> -	    (not:GPR (match_operand:GPR 1 "register_operand" "r"))
> -	    (match_operand:GPR 2 "register_operand" "r")))]
> +  [(set (match_operand:X 0 "register_operand" "=r")
> +	(neg_bitwise:X
> +	    (not:X (match_operand:X 1 "register_operand" "r"))
> +	    (match_operand:X 2 "register_operand" "r")))]
>    ""
>    "<insn>n\t%0,%2,%1"
>    [(set_attr "type" "logical")
>     (set_attr "mode" "<MODE>")])
>  
> +(define_insn "*<optab>nsi_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(neg_bitwise:SI
> +	    (not:SI (match_operand:SI 1 "register_operand" "r"))
> +	    (match_operand:SI 2 "register_operand" "r")))]
> +  "TARGET_64BIT"
> +  "<insn>n\t%0,%2,%1"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
>  \f
>  ;;
>  ;;  ....................
> @@ -3167,7 +3210,6 @@ (define_expand "condjump"
>  		      (label_ref (match_operand 1))
>  		      (pc)))])
>  
> -
>  \f
>  ;;
>  ;;  ....................
> @@ -3967,10 +4009,13 @@ (define_insn "bytepick_w_<bytepick_imm>"
>  (define_insn "bytepick_w_<bytepick_imm>_extend"
>    [(set (match_operand:DI 0 "register_operand" "=r")
>  	(sign_extend:DI
> -	  (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
> -			    (const_int <bytepick_w_lshiftrt_amount>))
> -		  (ashift (match_operand:SI 2 "register_operand" "r")
> -			  (const_int bytepick_w_ashift_amount)))))]
> +	 (subreg:SI
> +	  (ior:DI (subreg:DI (lshiftrt
> +			      (match_operand:SI 1 "register_operand" "r")
> +			      (const_int <bytepick_w_lshiftrt_amount>)) 0)
> +		  (subreg:DI (ashift
> +			      (match_operand:SI 2 "register_operand" "r")
> +			      (const_int bytepick_w_ashift_amount)) 0)) 0)))]
>    "TARGET_64BIT"
>    "bytepick.w\t%0,%1,%2,<bytepick_imm>"
>    [(set_attr "mode" "SI")])
> diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
> new file mode 100644
> index 00000000000..5753ef69db2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
> @@ -0,0 +1,21 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mabi=lp64d -O2" } */
> +/* { dg-final { scan-assembler-not "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" } } */
> +
> +struct pmop
> +{
> +  unsigned int op_pmflags;
> +  unsigned int op_pmpermflags;
> +};
> +unsigned int PL_hints;
> +
> +struct pmop *pmop;
> +void
> +Perl_newPMOP (int type, int flags)
> +{
> +  if (PL_hints & 0x00100000)
> +    pmop->op_pmpermflags |= 0x0001;
> +  if (PL_hints & 0x00000004)
> +    pmop->op_pmpermflags |= 0x0800;
> +  pmop->op_pmflags = pmop->op_pmpermflags;
> +}

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Re: [PATCH 3/3] LoongArch: Redundant sign extension elimination optimization 2.

[Xi Ruoyao]

On Sat, 2024-01-06 at 16:54 +0800, Lulu Cheng wrote:

/* snip */

> diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
> index a45dde4f73f..428535cb8e3 100644
> --- a/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
> +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
> @@ -1,6 +1,6 @@
>  /* { dg-do compile } */
>  /* { dg-options "-mabi=lp64d -O2" } */
> -/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */
> +/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 0 } } */

Use scan-assembler-not instead of scan-assembler-times ... 0.

Otherwise LGTM.

>  #include <stdint.h>
>  #define my_min(x, y) ((x) < (y) ? (x) : (y))

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Re: [pushed][PATCH 1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise operations.

[chenglulu]

Pushed to r14-7125.

在 2024/1/6 下午4:54, Lulu Cheng 写道:
> There are two mode iterators defined in the loongarch.md:
> 	(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
>    and
> 	(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
> Replace the mode in the bit arithmetic from GPR to X.
>
> Since the bitwise operation instruction does not distinguish between 64-bit,
> 32-bit, etc., it is necessary to perform symbolic expansion if the bitwise
> operation is less than 64 bits.
> The original definition would have generated a lot of redundant symbolic
> extension instructions. This problem is optimized with reference to the
> implementation of RISCV.
>
> Add this patch spec2017 500.perlbench performance improvement by 1.8%
>
> gcc/ChangeLog:
>
> 	* config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
> 	(*nor<mode>3): Likewise.
> 	(nor<mode>3): Likewise.
> 	(*negsi2_extended): New template.
> 	(*<optab>si3_internal): Likewise.
> 	(*one_cmplsi2_internal): Likewise.
> 	(*norsi3_internal): Likewise.
> 	(*<optab>nsi_internal): Likewise.
> 	(bytepick_w_<bytepick_imm>_extend): Modify this template according to the
> 	modified bit operation to make the optimization work.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/loongarch/sign-extend-bitwise.c: New test.
> ---
>   gcc/config/loongarch/loongarch.md             | 93 ++++++++++++++-----
>   .../loongarch/sign-extend-bitwise.c           | 21 +++++
>   2 files changed, 90 insertions(+), 24 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
>
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index d1f5b94f5d6..436b9a93235 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -736,7 +736,7 @@ (define_insn "sub<mode>3"
>   
>   (define_insn "sub<mode>3"
>     [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(minus:GPR (match_operand:GPR 1 "register_operand" "rJ")
> +	(minus:GPR (match_operand:GPR 1 "register_operand" "r")
>   		   (match_operand:GPR 2 "register_operand" "r")))]
>     ""
>     "sub.<d>\t%0,%z1,%2"
> @@ -1412,13 +1412,13 @@ (define_insn "neg<mode>2"
>     [(set_attr "alu_type"	"sub")
>      (set_attr "mode" "<MODE>")])
>   
> -(define_insn "one_cmpl<mode>2"
> -  [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(not:GPR (match_operand:GPR 1 "register_operand" "r")))]
> -  ""
> -  "nor\t%0,%.,%1"
> -  [(set_attr "alu_type" "not")
> -   (set_attr "mode" "<MODE>")])
> +(define_insn "*negsi2_extended"
> +  [(set (match_operand:DI 0 "register_operand" "=r")
> +	(sign_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))]
> +  "TARGET_64BIT"
> +  "sub.w\t%0,%.,%1"
> +  [(set_attr "alu_type" "sub")
> +   (set_attr "mode" "SI")])
>   
>   (define_insn "neg<mode>2"
>     [(set (match_operand:ANYF 0 "register_operand" "=f")
> @@ -1438,14 +1438,39 @@ (define_insn "neg<mode>2"
>   ;;
>   
>   (define_insn "<optab><mode>3"
> -  [(set (match_operand:GPR 0 "register_operand" "=r,r")
> -	(any_bitwise:GPR (match_operand:GPR 1 "register_operand" "%r,r")
> -			 (match_operand:GPR 2 "uns_arith_operand" "r,K")))]
> +  [(set (match_operand:X 0 "register_operand" "=r,r")
> +	(any_bitwise:X (match_operand:X 1 "register_operand" "%r,r")
> +		       (match_operand:X 2 "uns_arith_operand" "r,K")))]
>     ""
>     "<insn>%i2\t%0,%1,%2"
>     [(set_attr "type" "logical")
>      (set_attr "mode" "<MODE>")])
>   
> +(define_insn "*<optab>si3_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r,r")
> +	(any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r")
> +			(match_operand:SI 2 "uns_arith_operand"    " r,K")))]
> +  "TARGET_64BIT"
> +  "<insn>%i2\t%0,%1,%2"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
> +
> +(define_insn "one_cmpl<mode>2"
> +  [(set (match_operand:X 0 "register_operand" "=r")
> +	(not:X (match_operand:X 1 "register_operand" "r")))]
> +  ""
> +  "nor\t%0,%.,%1"
> +  [(set_attr "alu_type" "not")
> +   (set_attr "mode" "<MODE>")])
> +
> +(define_insn "*one_cmplsi2_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(not:SI (match_operand:SI 1 "register_operand" " r")))]
> +  "TARGET_64BIT"
> +  "nor\t%0,%.,%1"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
> +
>   (define_insn "and<mode>3_extended"
>     [(set (match_operand:GPR 0 "register_operand" "=r")
>   	(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "r")
> @@ -1561,25 +1586,43 @@ (define_insn "*iorhi3"
>     [(set_attr "type" "logical")
>      (set_attr "mode" "HI")])
>   
> -(define_insn "*nor<mode>3"
> -  [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "%r"))
> -		 (not:GPR (match_operand:GPR 2 "register_operand" "r"))))]
> +(define_insn "nor<mode>3"
> +  [(set (match_operand:X 0 "register_operand" "=r")
> +	(and:X (not:X (match_operand:X 1 "register_operand" "%r"))
> +		 (not:X (match_operand:X 2 "register_operand" "r"))))]
>     ""
>     "nor\t%0,%1,%2"
>     [(set_attr "type" "logical")
>      (set_attr "mode" "<MODE>")])
>   
> +(define_insn "*norsi3_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(and:SI (not:SI (match_operand:SI 1 "register_operand" "%r"))
> +		 (not:SI (match_operand:SI 2 "register_operand" "r"))))]
> +  "TARGET_64BIT"
> +  "nor\t%0,%1,%2"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
> +
>   (define_insn "<optab>n<mode>"
> -  [(set (match_operand:GPR 0 "register_operand" "=r")
> -	(neg_bitwise:GPR
> -	    (not:GPR (match_operand:GPR 1 "register_operand" "r"))
> -	    (match_operand:GPR 2 "register_operand" "r")))]
> +  [(set (match_operand:X 0 "register_operand" "=r")
> +	(neg_bitwise:X
> +	    (not:X (match_operand:X 1 "register_operand" "r"))
> +	    (match_operand:X 2 "register_operand" "r")))]
>     ""
>     "<insn>n\t%0,%2,%1"
>     [(set_attr "type" "logical")
>      (set_attr "mode" "<MODE>")])
>   
> +(define_insn "*<optab>nsi_internal"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +	(neg_bitwise:SI
> +	    (not:SI (match_operand:SI 1 "register_operand" "r"))
> +	    (match_operand:SI 2 "register_operand" "r")))]
> +  "TARGET_64BIT"
> +  "<insn>n\t%0,%2,%1"
> +  [(set_attr "type" "logical")
> +   (set_attr "mode" "SI")])
>   \f
>   ;;
>   ;;  ....................
> @@ -3167,7 +3210,6 @@ (define_expand "condjump"
>   		      (label_ref (match_operand 1))
>   		      (pc)))])
>   
> -
>   \f
>   ;;
>   ;;  ....................
> @@ -3967,10 +4009,13 @@ (define_insn "bytepick_w_<bytepick_imm>"
>   (define_insn "bytepick_w_<bytepick_imm>_extend"
>     [(set (match_operand:DI 0 "register_operand" "=r")
>   	(sign_extend:DI
> -	  (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
> -			    (const_int <bytepick_w_lshiftrt_amount>))
> -		  (ashift (match_operand:SI 2 "register_operand" "r")
> -			  (const_int bytepick_w_ashift_amount)))))]
> +	 (subreg:SI
> +	  (ior:DI (subreg:DI (lshiftrt
> +			      (match_operand:SI 1 "register_operand" "r")
> +			      (const_int <bytepick_w_lshiftrt_amount>)) 0)
> +		  (subreg:DI (ashift
> +			      (match_operand:SI 2 "register_operand" "r")
> +			      (const_int bytepick_w_ashift_amount)) 0)) 0)))]
>     "TARGET_64BIT"
>     "bytepick.w\t%0,%1,%2,<bytepick_imm>"
>     [(set_attr "mode" "SI")])
> diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
> new file mode 100644
> index 00000000000..5753ef69db2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
> @@ -0,0 +1,21 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mabi=lp64d -O2" } */
> +/* { dg-final { scan-assembler-not "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" } } */
> +
> +struct pmop
> +{
> +  unsigned int op_pmflags;
> +  unsigned int op_pmpermflags;
> +};
> +unsigned int PL_hints;
> +
> +struct pmop *pmop;
> +void
> +Perl_newPMOP (int type, int flags)
> +{
> +  if (PL_hints & 0x00100000)
> +    pmop->op_pmpermflags |= 0x0001;
> +  if (PL_hints & 0x00000004)
> +    pmop->op_pmpermflags |= 0x0800;
> +  pmop->op_pmflags = pmop->op_pmpermflags;
> +}