Re: rs6000: Fix expected counts powerpc/p9-vec-length-full

["Kewen.Lin" <linkw@linux.ibm.com>]

Hi Carl,

The issue was tracked by PR109971 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109971)
and I think it had been resolved.

btw, when the expected insn count changes, it does expose some
issues but which can be either test or functionality issue, if
it's taken as a test issue, it needs some justification why
it changes like that and the change is expected.

BR,
Kewen

on 2023/7/18 23:39, Carl Love wrote:
> Ping
> 
> On Thu, 2023-06-01 at 16:11 -0700, Carl Love wrote:
>> GCC maintainers:
>>
>> The following patch updates the expected instruction counts in four
>> tests.  The counts in all of the tests changed with commit
>> f574e2dfae79055f16d0c63cc12df24815d8ead6.  
>>
>> The updated counts have been verified on both Power 9 and Power 10.
>>
>> Please let me know if this patch is acceptable for mainline.  Thanks.
>>
>>                       Carl 
>>
>> --------------------
>> rs6000: Fix expected counts powerpc/p9-vec-length-full tests
>>
>> The counts for instructions lxvl and stxvl in tests:
>>
>>   p9-vec-length-full-1.c
>>   p9-vec-length-full-2.c
>>   p9-vec-length-full-6.c
>>   p9-vec-length-full-7.c
>>
>> changed with commit:
>>
>>    commit f574e2dfae79055f16d0c63cc12df24815d8ead6
>>    Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>>    Date:   Thu May 25 22:42:35 2023 +0800
>>
>>      VECT: Add decrement IV iteration loop control by variable amount
>> support
>>
>>      This patch is supporting decrement IV by following the flow
>> designed by
>>      Richard:
>>            ...
>>
>> The expected counts for lxvl changed from 20 to 40 and the counts for
>> stxvl
>> changed from 10 to 20 in the first three tests.  The number of stxvl
>> instructions changed from 12 to 20 in p9-vec-length-full-7.c.  This
>> patch updates the number of expected instructions in the four tests.
>>
>> The counts have been verified on Power 9 and Power 10.
>> ---
>>  gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c | 4 ++--
>>  gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c | 4 ++--
>>  gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c | 4 ++--
>>  gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c | 2 +-
>>  4 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c
>> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c
>> index f01f1c54fa5..5e4f34421d3 100644
>> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c
>> @@ -12,5 +12,5 @@
>>  /* { dg-final { scan-assembler-not   {\mstxv\M} } } */
>>  /* { dg-final { scan-assembler-not   {\mlxvx\M} } } */
>>  /* { dg-final { scan-assembler-not   {\mstxvx\M} } } */
>> -/* { dg-final { scan-assembler-times {\mlxvl\M} 20 } } */
>> -/* { dg-final { scan-assembler-times {\mstxvl\M} 10 } } */
>> +/* { dg-final { scan-assembler-times {\mlxvl\M} 40 } } */
>> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */
>> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c
>> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c
>> index f546e97fa7d..c7d927382c3 100644
>> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c
>> @@ -12,5 +12,5 @@
>>  /* { dg-final { scan-assembler-not   {\mstxv\M} } } */
>>  /* { dg-final { scan-assembler-not   {\mlxvx\M} } } */
>>  /* { dg-final { scan-assembler-not   {\mstxvx\M} } } */
>> -/* { dg-final { scan-assembler-times {\mlxvl\M} 20 } } */
>> -/* { dg-final { scan-assembler-times {\mstxvl\M} 10 } } */
>> +/* { dg-final { scan-assembler-times {\mlxvl\M} 40 } } */
>> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */
>> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c
>> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c
>> index 65ddf2b098a..f3be3842c62 100644
>> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c
>> @@ -11,5 +11,5 @@
>>  /* It can use normal vector load for constant vector load.  */
>>  /* { dg-final { scan-assembler-times {\mstxvx?\M} 6 } } */
>>  /* 64bit/32bit pairs won't use partial vectors.  */
>> -/* { dg-final { scan-assembler-times {\mlxvl\M} 10 } } */
>> -/* { dg-final { scan-assembler-times {\mstxvl\M} 10 } } */
>> +/* { dg-final { scan-assembler-times {\mlxvl\M} 20 } } */
>> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */
>> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
>> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
>> index e0e51d9a972..da086f1826a 100644
>> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
>> @@ -12,4 +12,4 @@
>>
>>  /* Each type has one stxvl excepting for int8 and uint8, that have
>> two due to
>>     rtl pass bbro duplicating the block which has one stxvl.  */
>> -/* { dg-final { scan-assembler-times {\mstxvl\M} 12 } } */
>> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */
>