From: Jeff Law <jeffreyalaw@gmail.com>
To: Sebastian Huber <sebastian.huber@embedded-brains.de>,
gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] riscv/RTEMS: Add RISCV_GCOV_TYPE_SIZE
Date: Thu, 27 Oct 2022 16:56:17 -0600 [thread overview]
Message-ID: <c834c2a9-c499-ffc5-8072-b9001e0715b8@gmail.com> (raw)
In-Reply-To: <20221026074950.10462-1-sebastian.huber@embedded-brains.de>
On 10/26/22 01:49, Sebastian Huber wrote:
> The RV32A extension does not support 64-bit atomic operations. For RTEMS, use
> a 32-bit gcov type for RV32.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_gcov_type_size): New.
> (TARGET_GCOV_TYPE_SIZE): Likewise.
> * config/riscv/rtems.h (RISCV_GCOV_TYPE_SIZE): New.
Why make this specific to rtems? ISTM the logic behind this change
would apply independently of the os.
jeff
next prev parent reply other threads:[~2022-10-27 22:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 7:49 Sebastian Huber
2022-10-27 22:56 ` Jeff Law [this message]
2022-10-27 23:05 ` Palmer Dabbelt
2022-10-28 5:47 ` Sebastian Huber
2022-11-01 15:52 ` Jeff Law
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