[PATCH v4, rs6000] Enable have_cbranchcc4 on rs6000

[PATCH v4, rs6000] Enable have_cbranchcc4 on rs6000

[HAO CHEN GUI]

Hi,
  This patch enables "have_cbranchcc4" on rs6000 by defining
a "cbranchcc4" expander. "have_cbrnachcc4" is a flag in ifcvt.cc
to indicate if branch by CC bits is invalid or not. With this
flag enabled, some branches can be optimized to conditional
moves.

  Compared to last version, the main changes are on the test
cases. Test case is renamed and comments are modified.

  Bootstrapped and tested on powerpc64-linux BE and LE with no
regressions. Is this okay for trunk? Any recommendations? Thanks
a lot.

BR
Gui Haochen

ChangeLog
2022-12-07  Haochen Gui <guihaoc@linux.ibm.com>

gcc/
	* config/rs6000/rs6000.md (cbranchcc4): New expander.

gcc/testsuite
	* gcc.target/powerpc/cbranchcc4-1.c: New.
	* gcc.target/powerpc/cbranchcc4-2.c: New.

patch.diff
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e9e5cd1e54d..d7ddd96cc70 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11932,6 +11932,16 @@ (define_expand "cbranch<mode>4"
   DONE;
 })

+(define_expand "cbranchcc4"
+  [(set (pc)
+	(if_then_else (match_operator 0 "branch_comparison_operator"
+			[(match_operand 1 "cc_reg_operand")
+			 (match_operand 2 "zero_constant")])
+		      (label_ref (match_operand 3))
+		      (pc)))]
+  ""
+  "")
+
 (define_expand "cstore<mode>4_signed"
   [(use (match_operator 1 "signed_comparison_operator"
          [(match_operand:P 2 "gpc_reg_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/cbranchcc4-1.c b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-1.c
new file mode 100644
index 00000000000..6c2cd130b6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Verify there is no ICE with cbranchcc4 enabled.  */
+
+int foo (double d)
+{
+  if (d == 0.0)
+    return 0;
+
+  d = ((d) >= 0 ? (d) : -(d));
+
+  if (d < 1.0)
+    return 1;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/cbranchcc4-2.c b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-2.c
new file mode 100644
index 00000000000..528ba1a878d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-rtl-ce1" } */
+/* { dg-final { scan-rtl-dump "noce_try_store_flag_constants" "ce1" } } */
+
+/* The inner branch should be detected by ifcvt then be converted to a setcc
+   with a plus by noce_try_store_flag_constants.  */
+
+int test (unsigned int a, unsigned int b)
+{
+    return (a < b ? 0 : (a > b ? 2 : 1));
+}

Re: [PATCH v4, rs6000] Enable have_cbranchcc4 on rs6000

[Kewen.Lin]

Hi Haochen,

on 2022/12/8 11:08, HAO CHEN GUI wrote:
> Hi,
>   This patch enables "have_cbranchcc4" on rs6000 by defining
> a "cbranchcc4" expander. "have_cbrnachcc4" is a flag in ifcvt.cc
> to indicate if branch by CC bits is invalid or not. With this
> flag enabled, some branches can be optimized to conditional
> moves.
> 
>   Compared to last version, the main changes are on the test
> cases. Test case is renamed and comments are modified.
> 
>   Bootstrapped and tested on powerpc64-linux BE and LE with no
> regressions. Is this okay for trunk? Any recommendations? Thanks
> a lot.
> 

This patch is OK, thanks!

BR,
Kewen

> BR
> Gui Haochen
> 
> ChangeLog
> 2022-12-07  Haochen Gui <guihaoc@linux.ibm.com>
> 
> gcc/
> 	* config/rs6000/rs6000.md (cbranchcc4): New expander.
> 
> gcc/testsuite
> 	* gcc.target/powerpc/cbranchcc4-1.c: New.
> 	* gcc.target/powerpc/cbranchcc4-2.c: New.
> 
> patch.diff
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index e9e5cd1e54d..d7ddd96cc70 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -11932,6 +11932,16 @@ (define_expand "cbranch<mode>4"
>    DONE;
>  })
> 
> +(define_expand "cbranchcc4"
> +  [(set (pc)
> +	(if_then_else (match_operator 0 "branch_comparison_operator"
> +			[(match_operand 1 "cc_reg_operand")
> +			 (match_operand 2 "zero_constant")])
> +		      (label_ref (match_operand 3))
> +		      (pc)))]
> +  ""
> +  "")
> +
>  (define_expand "cstore<mode>4_signed"
>    [(use (match_operator 1 "signed_comparison_operator"
>           [(match_operand:P 2 "gpc_reg_operand")
> diff --git a/gcc/testsuite/gcc.target/powerpc/cbranchcc4-1.c b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-1.c
> new file mode 100644
> index 00000000000..6c2cd130b6d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-1.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +/* Verify there is no ICE with cbranchcc4 enabled.  */
> +
> +int foo (double d)
> +{
> +  if (d == 0.0)
> +    return 0;
> +
> +  d = ((d) >= 0 ? (d) : -(d));
> +
> +  if (d < 1.0)
> +    return 1;
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/cbranchcc4-2.c b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-2.c
> new file mode 100644
> index 00000000000..528ba1a878d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/cbranchcc4-2.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fdump-rtl-ce1" } */
> +/* { dg-final { scan-rtl-dump "noce_try_store_flag_constants" "ce1" } } */
> +
> +/* The inner branch should be detected by ifcvt then be converted to a setcc
> +   with a plus by noce_try_store_flag_constants.  */
> +
> +int test (unsigned int a, unsigned int b)
> +{
> +    return (a < b ? 0 : (a > b ? 2 : 1));
> +}