From: Jeff Law <jeffreyalaw@gmail.com>
To: Andrew Pinski <apinski@marvell.com>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/2] Improve do_store_flag for single bit when there is no non-zero bits
Date: Tue, 6 Jun 2023 20:54:46 -0600 [thread overview]
Message-ID: <d2d7a875-e7bf-dcc4-b96a-aa406d4219a3@gmail.com> (raw)
In-Reply-To: <20230605055331.2864335-1-apinski@marvell.com>
On 6/4/23 23:53, Andrew Pinski via Gcc-patches wrote:
> In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
> turn off the bit tracking part of CCP so we would lose out
> what TER was able to do before hand. This moves around the
> TER code so that it is used instead of just the nonzerobits.
> It also makes it easier to remove the TER part of the code
> later on too.
Given that we want to kill TER, that seems like a good idea :-)
>
> OK? Bootstrapped and tested on x86_64-linux-gnu.
>
> Note it reintroduces PR 110117 (which was accidently fixed after
> r14-1534-g908e5ab5c11c). The next patch in series will fix that.
>
> gcc/ChangeLog:
>
> * expr.cc (do_store_flag): Rearrange the
> TER code so that it overrides the nonzero bits
> info if we had `a & POW2`.
OK.
jeff
prev parent reply other threads:[~2023-06-07 2:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 5:53 Andrew Pinski
2023-06-05 5:53 ` [PATCH 2/2] Handle const_int in expand_single_bit_test Andrew Pinski
2023-06-07 2:56 ` Jeff Law
2023-06-07 2:54 ` Jeff Law [this message]
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