* [PATCH PR81228][AARCH64][gcc-7] Backport r255625 : Fix ICE by adding LTGT
@ 2018-01-09 15:41 Sudakshina Das
2018-02-22 15:02 ` Sudakshina Das
0 siblings, 1 reply; 2+ messages in thread
From: Sudakshina Das @ 2018-01-09 15:41 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, James Greenhalgh, Richard Earnshaw, Marcus Shawcroft
[-- Attachment #1: Type: text/plain, Size: 923 bytes --]
Hi
This patch is only adding the missing LTGT to plug the ICE. This is a
backport to r255625 of trunk.
Testing done: Checked for regressions on bootstrapped
aarch64-none-linux-gnu and added a new compile time test case that gives
out LTGT to make sure it doesn't ICE.
Is this ok for trunk?
Thanks
Sudi
ChangeLog Entries:
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
Bin Cheng <bin.cheng@arm.com>
Backport from mainline:
2017-12-14 Sudakshina Das <sudi.das@arm.com>
Bin Cheng <bin.cheng@arm.com>
PR target/81228
* config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT to
CCFPEmode.
* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_cmp_result>): Add
LTGT.
*** gcc/testsuite/ChangeLog ***
2017-01-09 Sudakshina Das <sudi.das@arm.com>
Backport from mainline:
2017-12-14 Sudakshina Das <sudi.das@arm.com>
PR target/81228
* gcc.dg/pr81228.c: New.
[-- Attachment #2: rb8743.patch --]
[-- Type: text/x-patch, Size: 1928 bytes --]
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c462164..1e0a346 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2490,6 +2490,7 @@
case UNEQ:
case ORDERED:
case UNORDERED:
+ case LTGT:
break;
default:
gcc_unreachable ();
@@ -2544,6 +2545,15 @@
emit_insn (gen_one_cmpl<v_cmp_result>2 (operands[0], operands[0]));
break;
+ case LTGT:
+ /* LTGT is not guranteed to not generate a FP exception. So let's
+ go the faster way : ((a > b) || (b > a)). */
+ emit_insn (gen_aarch64_cmgt<mode> (operands[0],
+ operands[2], operands[3]));
+ emit_insn (gen_aarch64_cmgt<mode> (tmp, operands[3], operands[2]));
+ emit_insn (gen_ior<v_cmp_result>3 (operands[0], operands[0], tmp));
+ break;
+
case UNORDERED:
/* Operands are ORDERED iff (a > b || b >= a), so we can compute
UNORDERED as !ORDERED. */
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 436091a..db517ca 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4664,13 +4664,13 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
case UNGT:
case UNGE:
case UNEQ:
- case LTGT:
return CCFPmode;
case LT:
case LE:
case GT:
case GE:
+ case LTGT:
return CCFPEmode;
default:
diff --git a/gcc/testsuite/gcc.dg/pr81228.c b/gcc/testsuite/gcc.dg/pr81228.c
new file mode 100644
index 0000000..f7eecc5
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr81228.c
@@ -0,0 +1,21 @@
+/* PR target/81228. */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-tree-ssa" } */
+
+void *a;
+
+void b ()
+{
+ char c;
+ long d;
+ char *e = a;
+ for (; d; d++)
+ {
+ double f, g;
+ c = g < f || g > f;
+ e[d] = c;
+ }
+}
+
+/* Let's make sure we do have a LTGT. */
+/* { dg-final { scan-tree-dump "<>" "ssa" } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH PR81228][AARCH64][gcc-7] Backport r255625 : Fix ICE by adding LTGT
2018-01-09 15:41 [PATCH PR81228][AARCH64][gcc-7] Backport r255625 : Fix ICE by adding LTGT Sudakshina Das
@ 2018-02-22 15:02 ` Sudakshina Das
0 siblings, 0 replies; 2+ messages in thread
From: Sudakshina Das @ 2018-02-22 15:02 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, James Greenhalgh, Richard Earnshaw, Marcus Shawcroft
On 09/01/18 15:37, Sudakshina Das wrote:
> Hi
>
> This patch is only adding the missing LTGT to plug the ICE. This is a
> backport to r255625 of trunk.
>
> Testing done: Checked for regressions on bootstrapped
> aarch64-none-linux-gnu and added a new compile time test case that gives
> out LTGT to make sure it doesn't ICE.
>
> Is this ok for trunk?
>
Backported to gcc-7 as r257901.
Sudi
> Thanks
> Sudi
>
> ChangeLog Entries:
>
> *** gcc/ChangeLog ***
>
> 2018-01-09 Sudakshina Das <sudi.das@arm.com>
>        Bin Cheng <bin.cheng@arm.com>
>
> Â Â Â Â Backport from mainline:
>     2017-12-14 Sudakshina Das <sudi.das@arm.com>
>                Bin Cheng <bin.cheng@arm.com>
>
> Â Â Â Â PR target/81228
> Â Â Â Â * config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT to
> CCFPEmode.
> Â Â Â Â * config/aarch64/aarch64-simd.md (vec_cmp<mode><v_cmp_result>): Add
> Â Â Â Â LTGT.
>
> *** gcc/testsuite/ChangeLog ***
>
> 2017-01-09 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â Backport from mainline:
>     2017-12-14 Sudakshina Das <sudi.das@arm.com>
>
> Â Â Â Â PR target/81228
> Â Â Â Â * gcc.dg/pr81228.c: New.
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