From: Alexander Monakov <amonakov@ispras.ru>
To: Hongtao Liu <crazylht@gmail.com>
Cc: "Liu, Hongtao" <hongtao.liu@intel.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] Add a bit dislike for separate mem alternative when op is REG_P.
Date: Mon, 30 May 2022 12:41:57 +0300 (MSK) [thread overview]
Message-ID: <f7c06893-733f-702d-8a6e-8ec52f026a@ispras.ru> (raw)
In-Reply-To: <CAMZc-bwGmgiDVkJuKhRS22HdV7H7fGXAwfu_-_+5ARVZ7GOghw@mail.gmail.com>
On Mon, 30 May 2022, Hongtao Liu wrote:
> On Mon, May 30, 2022 at 3:44 PM Alexander Monakov <amonakov@ispras.ru> wrote:
> >
> > On Mon, 30 May 2022, Hongtao Liu wrote:
> >
> > > On Mon, May 30, 2022 at 2:22 PM Alexander Monakov via Gcc-patches
> > > <gcc-patches@gcc.gnu.org> wrote:
> > > > >
> > > > > The spill is mainly decided by 3 insns related to r92
> > > > >
> > > > > 283(insn 3 61 4 2 (set (reg/v:SF 92 [ x ])
> > > > > 284 (reg:SF 102)) "test3.c":7:1 142 {*movsf_internal}
> > > > > 285 (expr_list:REG_DEAD (reg:SF 102)
> > > > >
> > > > > 288(insn 9 4 12 2 (set (reg:SI 89 [ _11 ])
> > > > > 289 (subreg:SI (reg/v:SF 92 [ x ]) 0)) "test3.c":3:36 81 {*movsi_internal}
> > > > > 290 (nil))
> > > > >
> > > > > And
> > > > > 382(insn 28 27 29 5 (set (reg:DF 98)
> > > > > 383 (float_extend:DF (reg/v:SF 92 [ x ]))) "test3.c":11:13 163 {*extendsfdf2}
> > > > > 384 (expr_list:REG_DEAD (reg/v:SF 92 [ x ])
> > > > > 385 (nil)))
> > > > > 386(insn 29 28 30 5 (s
> > > > >
> > > > > The frequency the for INSN 3 and INSN 9 is not affected, but frequency of INSN
> > > > > 28 drop from 805 -> 89 after swapping "unlikely" and "likely". Because of
> > > > > that, GPR cost decreases a lot, finally make the RA choose GPR instead of MEM.
> > > > >
> > > > > GENERAL_REGS:2356,2356
> > > > > SSE_REGS:6000,6000
> > > > > MEM:4089,4089
> > > >
> > > > But why are SSE_REGS costed so high? r92 is used in SFmode, it doesn't make
> > > > sense that selecting a GPR for it looks cheaper than xmm0.
> > > For INSN3 and INSN 28, SSE_REGS costs zero.
> > > But for INSN 9, it's a SImode move, we have disparaged non-gpr
> > > alternatives in movsi_internal pattern which finally makes SSE_REGS
> > > costs 6 * 1000(1000 is frequency, 6 is move cost between SSE_REGS and
> > > GPR, sse_to_integer/integer_to_sse).
> >
> > But wait, selecting a GPR for r92 makes insn 3 (movsf_internal) an
> > sse-to-integer move, so it should be equally high cost? Not to mention
> > that the use in insn 28 (extendsfdf2) should have higher cost also.
> >
> > Why does GPR cost 2356 instead of 6000 for insn 3 plus extra for insn 28?
> First GPR cost in insn 3 is not necessarily equal to integer_to_sse,
> it's the minimal cost of all alternatives, and one alternative is ?r,
> the cost is 2.
>
> I think the difference in movsf_internal and movsi_internal for *v and
> ?r make RA finally choose GPR.
I think this is one of the main issues here, if in the end it's the same
'mov %xmmN, <gpr>' instruction, only the pattern name is different.
Alexander
prev parent reply other threads:[~2022-05-30 9:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 3:39 liuhongt
2022-05-25 5:17 ` Hongtao Liu
2022-05-26 21:12 ` Vladimir Makarov
2022-05-30 3:05 ` Hongtao Liu
2022-05-31 16:28 ` Vladimir Makarov
2022-05-31 16:40 ` Richard Sandiford
2022-05-31 23:51 ` Hongtao Liu
2022-05-27 9:39 ` Alexander Monakov
2022-05-30 2:52 ` Liu, Hongtao
2022-05-30 6:22 ` Alexander Monakov
2022-05-30 7:14 ` Hongtao Liu
2022-05-30 7:44 ` Alexander Monakov
2022-05-30 8:34 ` Hongtao Liu
2022-05-30 9:41 ` Alexander Monakov [this message]
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