[PATCH v1 0/1] RISC-V: Nan-box the result of movbf on soft-bf16

[PATCH v1 0/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Xiao Zeng]

Compared to the initial patch:
<https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650864.html>

1 Fixed the formatting issue, although the modified format can pass the
CI format check, it looks strange.

2 Due to CI not using the latest code for patch, the initial patch build failed.

3 V1 submission will trigger CI again, hoping to resolve this issue. If not, I will
send an email to the CI management personnel requesting them to manually run it.

4 For information about CI, you can refer to the following email conversation:
-----------------------------------------------------------------------------------------------
On 5/7/24 01:25, Xiao Zeng wrote:
> Hi, during the use of CI, I discovered a possible issue and am now providing feedback to you
>
> https://github.com/ewlu/gcc-precommit-ci/issues/1481
>
> The RISCV_Nanbox_the_result_of_movbf_on_softbf16 relies on the mainline with a CommitID
> of <8c7cee80eb50792e57d514be1418c453ddd1073e>, but in CI, <ec1cdad> is used as the
> parent CommitID, which obviously leads to patch compilation failure.
>
> Expect that each CI is performed on the latest code.
>
> Of course, perhaps there are other considerations here.
>
> How can I operate to enable CI to use the latest mainline code?
>
> Looking forward to your reply very much.
>
> Thanks
> Xiao Zeng
>
Hi Xiao,

Thanks for reaching out.

Currently we rely on postcommit generate a baseline of known failures:

https://github.com/patrick-rivos/gcc-postcommit-ci/issues

Precommit then applies patches to that same baseline hash and compares
the results.

We don't currently have enough compute to generate a baseline for each
patch sent to the mailing list. We'll be asking for more compute from
the RISE project in the next week or so to allow us to use the most
recent GCC hash.

What you noticed yesterday was a bad change to the postcommit-CI which
prevented a new baseline from being generated.

It's expected that precommit uses a ~8 hour old commit as a baseline. If
a patch ever requires a recent commit, feel free to email us and we'll
rerun the precommit CI once a new baseline exists.

We should have a new baseline in ~8 hours and I'll rerun your patch for
you once that happens.

Thanks,
Patrick
-----------------------------------------------------------------------------------------------

Xiao Zeng (1):
  RISC-V: Nan-box the result of movbf on soft-bf16

 gcc/config/riscv/riscv.cc                     | 51 ++++++++++---------
 gcc/config/riscv/riscv.md                     | 12 ++++-
 .../gcc.target/riscv/_Bfloat16-nanboxing.c    | 38 ++++++++++++++
 3 files changed, 76 insertions(+), 25 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c

-- 
2.17.1

[PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Xiao Zeng]

1 This patch implements the Nan-box of bf16.

2 Please refer to the Nan-box implementation of hf16 in:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=057dc349021660c40699fb5c98fd9cac8e168653>

3 The discussion about Nan-box can be found on the website:
<https://www.mail-archive.com/search?q=Nan-box+the+result+of+movhf+on+soft-fp16&l=gcc-patches%40gcc.gnu.org>

4 Below test are passed for this patch
        * The riscv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf
	with Nan-boxing value.
	* config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/_Bfloat16-nanboxing.c: New test.
---
 gcc/config/riscv/riscv.cc                     | 51 ++++++++++---------
 gcc/config/riscv/riscv.md                     | 12 ++++-
 .../gcc.target/riscv/_Bfloat16-nanboxing.c    | 38 ++++++++++++++
 3 files changed, 76 insertions(+), 25 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 545e68566dc..be2cb245733 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3120,35 +3120,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
     }
 
   /* In order to fit NaN boxing, expand
-     (set FP_REG (reg:HF src))
+     (set FP_REG (reg:HF/BF src))
      to
      (set (reg:SI/DI mask) (const_int -65536)
-     (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF src) 0)))
+     (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0)))
      (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
-     (set (reg:HF dest) (unspec:HF [ (reg:SI/DI temp) ] UNSPEC_FMV_SFP16_X))
+     (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ]
+			    UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X))
      */
 
- if (TARGET_HARD_FLOAT
-     && !TARGET_ZFHMIN && mode == HFmode
-     && REG_P (dest) && FP_REG_P (REGNO (dest))
-     && REG_P (src) && !FP_REG_P (REGNO (src))
-     && can_create_pseudo_p ())
-   {
-     rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
-     rtx temp = gen_reg_rtx (word_mode);
-     emit_insn (gen_extend_insn (temp,
-				 simplify_gen_subreg (HImode, src, mode, 0),
-				 word_mode, HImode, 1));
-     if (word_mode == SImode)
-       emit_insn (gen_iorsi3 (temp, mask, temp));
-     else
-       emit_insn (gen_iordi3 (temp, mask, temp));
-
-     riscv_emit_move (dest, gen_rtx_UNSPEC (HFmode, gen_rtvec (1, temp),
-					    UNSPEC_FMV_SFP16_X));
-
-     return true;
-   }
+  if (TARGET_HARD_FLOAT
+      && ((!TARGET_ZFHMIN && mode == HFmode)
+	  || (!TARGET_ZFBFMIN && mode == BFmode))
+      && REG_P (dest) && FP_REG_P (REGNO (dest)) && REG_P (src)
+      && !FP_REG_P (REGNO (src)) && can_create_pseudo_p ())
+    {
+      rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
+      rtx temp = gen_reg_rtx (word_mode);
+      emit_insn (gen_extend_insn (temp,
+				  simplify_gen_subreg (HImode, src, mode, 0),
+				  word_mode, HImode, 1));
+      if (word_mode == SImode)
+	emit_insn (gen_iorsi3 (temp, mask, temp));
+      else
+	emit_insn (gen_iordi3 (temp, mask, temp));
+
+      riscv_emit_move (dest,
+		       gen_rtx_UNSPEC (mode, gen_rtvec (1, temp),
+				       mode == HFmode ? UNSPEC_FMV_SFP16_X
+						      : UNSPEC_FMV_SBF16_X));
+
+      return true;
+    }
 
   /* We need to deal with constants that would be legitimate
      immediate_operands but aren't legitimate move_operands.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 24558682eb8..236293e2fcd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -86,8 +86,9 @@
   ;; String unspecs
   UNSPEC_STRLEN
 
-  ;; Workaround for HFmode without hardware extension
+  ;; Workaround for HFmode and BFmode without hardware extension
   UNSPEC_FMV_SFP16_X
+  UNSPEC_FMV_SBF16_X
 
   ;; XTheadFmv moves
   UNSPEC_XTHEADFMV
@@ -1926,6 +1927,15 @@
   [(set_attr "type" "fmove")
    (set_attr "mode" "SF")])
 
+(define_insn "*movbf_softfloat_boxing"
+  [(set (match_operand:BF 0 "register_operand"		  "=f")
+	(unspec:BF [(match_operand:X 1 "register_operand" " r")]
+	 UNSPEC_FMV_SBF16_X))]
+  "!TARGET_ZFBFMIN"
+  "fmv.w.x\t%0,%1"
+  [(set_attr "type" "fmove")
+   (set_attr "mode" "SF")])
+
 ;;
 ;;  ....................
 ;;
diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
new file mode 100644
index 00000000000..11a73d22234
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */
+
+_Bfloat16 gvar = 9.87654;
+union U
+{
+  unsigned short i16;
+  _Bfloat16 f16;
+};
+
+_Bfloat16
+test1 (unsigned short input)
+{
+  union U tmp;
+  tmp.i16 = input;
+  return tmp.f16;
+}
+
+_Bfloat16
+test2 ()
+{
+  return 1.234f;
+}
+
+_Bfloat16
+test3 ()
+{
+  return gvar;
+}
+
+_Bfloat16
+test ()
+{
+  return 0.0f;
+}
+
+/* { dg-final { scan-assembler-times "li\[ \t\]" 4 } } */
+/* { dg-final { scan-assembler-times "fmv\.w\.x\[ \t\]" 4 } } */
-- 
2.17.1

Re: [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Jeff Law]

On 5/7/24 6:38 PM, Xiao Zeng wrote:
> 1 This patch implements the Nan-box of bf16.
> 
> 2 Please refer to the Nan-box implementation of hf16 in:
> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=057dc349021660c40699fb5c98fd9cac8e168653>
> 
> 3 The discussion about Nan-box can be found on the website:
> <https://www.mail-archive.com/search?q=Nan-box+the+result+of+movhf+on+soft-fp16&l=gcc-patches%40gcc.gnu.org>
> 
> 4 Below test are passed for this patch
>          * The riscv fully regression test.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf
> 	with Nan-boxing value.
> 	* config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/_Bfloat16-nanboxing.c: New test.
> ---
>   gcc/config/riscv/riscv.cc                     | 51 ++++++++++---------
>   gcc/config/riscv/riscv.md                     | 12 ++++-
>   .../gcc.target/riscv/_Bfloat16-nanboxing.c    | 38 ++++++++++++++
>   3 files changed, 76 insertions(+), 25 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
> 
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 545e68566dc..be2cb245733 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3120,35 +3120,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)

>   
> - if (TARGET_HARD_FLOAT
> -     && !TARGET_ZFHMIN && mode == HFmode
> -     && REG_P (dest) && FP_REG_P (REGNO (dest))
> -     && REG_P (src) && !FP_REG_P (REGNO (src))
> -     && can_create_pseudo_p ())
[ ... ]

> +  if (TARGET_HARD_FLOAT
> +      && ((!TARGET_ZFHMIN && mode == HFmode)
> +	  || (!TARGET_ZFBFMIN && mode == BFmode))
> +      && REG_P (dest) && FP_REG_P (REGNO (dest)) && REG_P (src)
> +      && !FP_REG_P (REGNO (src)) && can_create_pseudo_p ())

So there's a bit of gratutious rewriting going on here.  I realize you 
were fixing formatting problems (thanks!), but I don't see a need to 
rewriting the tests starting with REG_P.  I put those back in their 
original form with the whitespace fixes.

I'll push the fixed version momentarily.

Thanks again!

jeff

Re: Re: [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Xiao Zeng]

2024-05-09 04:01  Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
>On 5/7/24 6:38 PM, Xiao Zeng wrote:
>> 1 This patch implements the Nan-box of bf16.
>>
>> 2 Please refer to the Nan-box implementation of hf16 in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=057dc349021660c40699fb5c98fd9cac8e168653>
>>
>> 3 The discussion about Nan-box can be found on the website:
>> <https://www.mail-archive.com/search?q=Nan-box+the+result+of+movhf+on+soft-fp16&l=gcc-patches%40gcc.gnu.org>
>>
>> 4 Below test are passed for this patch
>>          * The riscv fully regression test.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf
>> with Nan-boxing value.
>> * config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/_Bfloat16-nanboxing.c: New test.
>> ---
>>   gcc/config/riscv/riscv.cc                     | 51 ++++++++++---------
>>   gcc/config/riscv/riscv.md                     | 12 ++++-
>>   .../gcc.target/riscv/_Bfloat16-nanboxing.c    | 38 ++++++++++++++
>>   3 files changed, 76 insertions(+), 25 deletions(-)
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 545e68566dc..be2cb245733 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -3120,35 +3120,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
>
>>  
>> - if (TARGET_HARD_FLOAT
>> -     && !TARGET_ZFHMIN && mode == HFmode
>> -     && REG_P (dest) && FP_REG_P (REGNO (dest))
>> -     && REG_P (src) && !FP_REG_P (REGNO (src))
>> -     && can_create_pseudo_p ())
>[ ... ]
>
>> +  if (TARGET_HARD_FLOAT
>> +      && ((!TARGET_ZFHMIN && mode == HFmode)
>> +	  || (!TARGET_ZFBFMIN && mode == BFmode))
>> +      && REG_P (dest) && FP_REG_P (REGNO (dest)) && REG_P (src)
>> +      && !FP_REG_P (REGNO (src)) && can_create_pseudo_p ())
>
>So there's a bit of gratutious rewriting going on here.  I realize you
>were fixing formatting problems (thanks!), 
> but I don't see a need to rewriting the tests starting with REG_P.  I put those back in their
>original form with the whitespace fixes. 
Thanks

>
>I'll push the fixed version momentarily. 
Thanks

>
>Thanks again!
>
>jeff
> 
In the past few days, I have been on vacation. Okay, let's continue to push forward with bf16.

Thanks
Xiao Zeng