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From: Jeff Law <jeffreyalaw@gmail.com>
To: "Christoph Müllner" <christoph.muellner@vrull.eu>
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	Cooper Qu <cooper.qu@linux.alibaba.com>,
	Lifang Xia <lifang_xia@linux.alibaba.com>,
	Yunhai Shang <yunhai@linux.alibaba.com>,
	Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 10/11] riscv: thead: Add support for the XTheadMemIdx ISA extension
Date: Thu, 29 Jun 2023 08:09:27 -0600	[thread overview]
Message-ID: <f9e5749e-4305-b9c7-b9b0-bacf00bd5c8d@gmail.com> (raw)
In-Reply-To: <CAEg0e7gA8kPs-YPG==oVtaj8buHsGF3jYOt4mr82Uy95oODWrA@mail.gmail.com>



On 6/29/23 01:39, Christoph Müllner wrote:
> On Wed, Jun 28, 2023 at 8:23 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 6/28/23 06:39, Christoph Müllner wrote:
>>
>>>>> +;; XTheadMemIdx overview:
>>>>> +;; All peephole passes attempt to improve the operand utilization of
>>>>> +;; XTheadMemIdx instructions, where one sign or zero extended
>>>>> +;; register-index-operand can be shifted left by a 2-bit immediate.
>>>>> +;;
>>>>> +;; The basic idea is the following optimization:
>>>>> +;; (set (reg 0) (op (reg 1) (imm 2)))
>>>>> +;; (set (reg 3) (mem (plus (reg 0) (reg 4)))
>>>>> +;; ==>
>>>>> +;; (set (reg 3) (mem (plus (reg 4) (op2 (reg 1) (imm 2))))
>>>>> +;; This optimization only valid if (reg 0) has no further uses.
>>>> Couldn't this be done by combine if you created define_insn patterns
>>>> rather than define_peephole2 patterns?  Similarly for the other cases
>>>> handled here.
>>>
>>> I was inspired by XTheadMemPair, which merges two memory accesses
>>> into a mem-pair instruction (and which got inspiration from
>>> gcc/config/aarch64/aarch64-ldpstp.md).
>> Right.  I'm pretty familiar with those.  They cover a different case,
>> specifically the two insns being optimized don't have a true data
>> dependency between them.  ie, the first instruction does not produce a
>> result used in the second insn.
>>
>>
>> In the case above there is a data dependency on reg0.  ie, the first
>> instruction generates a result used in the second instruction.  combine
>> is usually the best place to handle the data dependency case.
> 
> Ok, understood.
> 
> It is a bit of a special case here, because the peephole is restricted
> to those cases, where reg0 is not used elsewhere (peep2_reg_dead_p()).
> I have not seen how to do this for combiner optimizations.
If the value is used elsewhere, then the combiner will generate a 
parallel with two sets.  If the value dies, then the combiner generates 
the one set.  ie given

(set (t) (op0 (a) (b)))
(set (r) (op1 (c) (t)))

If "t" is dead, then combine will present you with:

(set (r) (op1 (c) (op0 (a) (b))))

If "t" is used elsewhere, then combine will present you with:

(parallel
   [(set (r) (op1 (c) (op0 (a) (b))))
    (set (t) (op0 (a) (b)))])

Which makes perfect sense if you think about it for a while.  If you 
still need "t", then the first sequence simply isn't valid as it doesn't 
preserve that side effect.  Hence it tries to produce a sequence with 
the combined operation, but with the side effect of the first statement 
included as well.


Jeff

  reply	other threads:[~2023-06-29 14:09 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-28  6:23 Christoph Muellner
2023-04-28  6:23 ` [PATCH 11/11] riscv: thead: Add support for the XTheadFMemIdx " Christoph Muellner
2023-06-10 17:54   ` Jeff Law
2023-06-28 12:39     ` Christoph Müllner
2023-06-10 17:53 ` [PATCH 10/11] riscv: thead: Add support for the XTheadMemIdx " Jeff Law
2023-06-28 12:39   ` Christoph Müllner
2023-06-28 18:23     ` Jeff Law
2023-06-29  7:39       ` Christoph Müllner
2023-06-29 14:09         ` Jeff Law [this message]
2023-07-06  6:48           ` Christoph Müllner
2023-07-06 15:28             ` Jeff Law

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