Re: [PATCH] RISC-V: Add attributes for VSETVL PASS

[Palmer Dabbelt <palmer@dabbelt.com>]

On Mon, 28 Nov 2022 20:49:00 PST (-0800), jeffreyalaw@gmail.com wrote:
>
>
> On 11/28/22 19:56, Palmer Dabbelt wrote:
>> On Mon, 28 Nov 2022 17:46:16 PST (-0800), juzhe.zhong@rivai.ai wrote:
>>> Yeah, I personally want to support RVV intrinsics in GCC13. As RVV
>>> intrinsic is going to release soon next week.
>>
>> OK, that's fine with me -- I was leaning that way, and I think Jeff only
>> had a weak opposition.  Are there any more changes required outside the
>> RISC-V backend?  Those would be the most controversial and are already
>> late, but if it's only backend stuff at this point then I'm OK taking
>> the risk for a bit longer.
>>
>> Jeff?
> It's not ideal, but I can live with the bits going into gcc-13 as long
> as they don't bleed out of the RISC-V port.

Ya, that's kind of what happens every release though (and not just in 
GCC, it's that way for everything).  Maybe for gcc-14 we can commit to 
taking the stage1/stage3 split seriously in RISC-V land?

It's early enough that nobody should be surprised, and even if we don't 
need to do it as per the GCC rules we're going to go crazy if we keep 
letting things go until the last minute like this.  I think the only 
real fallout we've had so far was the B stuff in binutils, but we've 
been exceedingly close to broken releases way too many times and it's 
going to bite us at some point.