Re: [PATCH v3] RISC-V: Libitm add RISC-V support.

[Palmer Dabbelt <palmer@dabbelt.com>]

On Fri, 28 Oct 2022 02:37:13 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> I guess we don't really care about RV32E here, but in case you add a
> guard for that?
>
> #ifdef __riscv_e
> #error "rv32e unsupported"
> #endif

Ah, thanks.  There's rv64e now too, but that's just an error message 
problem so probably not a big deal.

> On Fri, Oct 28, 2022 at 4:39 PM Xiongchuan Tan via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
>>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> libitm/ChangeLog:
>>
>>         * configure.tgt: Add riscv support.
>>         * config/riscv/asm.h: New file.
>>         * config/riscv/sjlj.S: New file.
>>         * config/riscv/target.h: New file.
>> ---
>> v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
>> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)
>>
>> v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in
>> cpu_relax()
>>
>>  libitm/config/riscv/asm.h    |  54 +++++++++++++
>>  libitm/config/riscv/sjlj.S   | 144 +++++++++++++++++++++++++++++++++++
>>  libitm/config/riscv/target.h |  62 +++++++++++++++
>>  libitm/configure.tgt         |   2 +
>>  4 files changed, 262 insertions(+)
>>  create mode 100644 libitm/config/riscv/asm.h
>>  create mode 100644 libitm/config/riscv/sjlj.S
>>  create mode 100644 libitm/config/riscv/target.h
>>
>> diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h
>> new file mode 100644
>> index 0000000..bb515f2
>> --- /dev/null
>> +++ b/libitm/config/riscv/asm.h
>> @@ -0,0 +1,54 @@
>> +/* Copyright (C) 2022 Free Software Foundation, Inc.
>> +   Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
>> +
>> +   This file is part of the GNU Transactional Memory Library (libitm).
>> +
>> +   Libitm is free software; you can redistribute it and/or modify it
>> +   under the terms of the GNU General Public License as published by
>> +   the Free Software Foundation; either version 3 of the License, or
>> +   (at your option) any later version.
>> +
>> +   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
>> +   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
>> +   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> +   more details.
>> +
>> +   Under Section 7 of GPL version 3, you are granted additional
>> +   permissions described in the GCC Runtime Library Exception, version
>> +   3.1, as published by the Free Software Foundation.
>> +
>> +   You should have received a copy of the GNU General Public License and
>> +   a copy of the GCC Runtime Library Exception along with this program;
>> +   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
>> +   <http://www.gnu.org/licenses/>.  */
>> +
>> +#ifndef _RV_ASM_H
>> +#define _RV_ASM_H
>> +
>> +#if __riscv_xlen == 64
>> +#  define GPR_L ld
>> +#  define GPR_S sd
>> +#  define SZ_GPR 8
>> +#  define LEN_GPR 14
>> +#elif __riscv_xlen == 32
>> +#  define GPR_L lw
>> +#  define GPR_S sw
>> +#  define SZ_GPR 4
>> +#  define LEN_GPR 16 /* Extra padding to align the stack to 16 bytes */
>> +#else
>> +#  error Unsupported XLEN (must be 64-bit or 32-bit).
>> +#endif
>> +
>> +#if defined(__riscv_flen) && __riscv_flen == 64
>> +#  define FPR_L fld
>> +#  define FPR_S fsd
>> +#  define SZ_FPR 8
>> +#elif defined(__riscv_flen) && __riscv_flen == 32
>> +#  define FPR_L flw
>> +#  define FPR_S fsw
>> +#  define SZ_FPR 4
>
> Check __riscv_flen is not 32 or 64 here, in case we add Q-extension
> then we can error out.
>
>> diff --git a/libitm/config/riscv/sjlj.S b/libitm/config/riscv/sjlj.S
>> new file mode 100644
>> index 0000000..93f12ec
>> --- /dev/null
>> +++ b/libitm/config/riscv/sjlj.S
>> @@ -0,0 +1,144 @@
>> +#include "asmcfi.h"
>> +#include "asm.h"
>> +
>> +       .text
>> +       .align  2
>> +       .global _ITM_beginTransaction
>> +       .type   _ITM_beginTransaction, @function
>> +
>> +_ITM_beginTransaction:
>> +       cfi_startproc
>> +       mv a1, sp
>> +       addi sp, sp, -(LEN_GPR*SZ_GPR+ 12*SZ_FPR)
>
> This expression appeared 4 times, maybe define a marco ADJ_STACK_SIZE
> or something else to hold that?
>
>> +       cfi_adjust_cfa_offset(LEN_GPR*SZ_GPR+ 12*SZ_FPR)
>
>> diff --git a/libitm/config/riscv/target.h b/libitm/config/riscv/target.h
>> new file mode 100644
>> index 0000000..b8a1665
>> --- /dev/null
>> +++ b/libitm/config/riscv/target.h
>> @@ -0,0 +1,62 @@
>> +typedef struct gtm_jmpbuf
>> +  {
>> +    long int pc;
>> +    void *cfa;
>> +    long int s[12]; /* Saved registers, s0 is fp */
>> +
>> +#if __riscv_xlen == 32
>> +    /* Ensure that the stack is 16-byte aligned */
>> +    long int padding[2];
>> +#endif
>> +
>> +    /* FP saved registers */
>> +#if defined(__riscv_flen) && __riscv_flen == 64
>> +    double fs[12];
>> +#elif defined(__riscv_flen) && __riscv_flen == 32
>> +    float fs[12];
>
> Same here, error __riscv_flen if defined but not 64 or 32.