From: Palmer Dabbelt <palmer@dabbelt.com>
To: gcc-patches@gcc.gnu.org
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@gmail.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>
Subject: Re: [PATCH] testsuite: adjust patterns in RISC-V tests to skip unwind table directives
Date: Thu, 09 Feb 2023 11:09:26 -0800 (PST) [thread overview]
Message-ID: <mhng-e35de886-7d83-4510-887b-30ff2faf866b@palmer-ri-x1c9a> (raw)
In-Reply-To: <mvmfsbfuq3a.fsf@suse.de>
On Thu, 09 Feb 2023 01:48:25 PST (-0800), gcc-patches@gcc.gnu.org wrote:
> PR target/108723
> * gcc.target/riscv/shorten-memrefs-1.c: Adjust patterns to skip
> over cfi directives.
> * gcc.target/riscv/shorten-memrefs-2.c: Likewise.
> * gcc.target/riscv/shorten-memrefs-3.c: Likewise.
> * gcc.target/riscv/shorten-memrefs-4.c: Likewise.
> * gcc.target/riscv/shorten-memrefs-5.c: Likewise.
> * gcc.target/riscv/shorten-memrefs-6.c: Likewise.
> * gcc.target/riscv/shorten-memrefs-8.c: Likewise.
> ---
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 8 ++++----
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 8 ++++----
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c | 2 +-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 4 ++--
> 7 files changed, 16 insertions(+), 16 deletions(-)
It kind of smells like there's some better way to write these test
cases, but the label->instruction matching was already there. I'm fine
just taking the fix for now so
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
but if anyone has ideas on how to make the tests less fragile I'm all
ears.
I didn't actually run the tests and I'm pretty bad at doing regexes in
my head, though. If you ran them and can commit that's good with me,
but LMK if you want me to.
Thanks!
>
> diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> index f0222f46eff..cce7c80f6c1 100644
> --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> @@ -23,5 +23,5 @@ store2z (long long *array)
> array[203] = 0;
> }
>
> -/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
> -/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
> +/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
> +/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> index ec39104fd88..a9ddb797d06 100644
> --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> @@ -44,9 +44,9 @@ load2r (long long *array)
> return a;
> }
>
> -/* { dg-final { scan-assembler "store1a:\n\taddi" } } */
> +/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> /* The sd insns in store2a are not rewritten because shorten_memrefs currently
> only optimizes lw and sw.
> -/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-* } } } */
> -/* { dg-final { scan-assembler "load1r:\n\taddi" } } */
> -/* { dg-final { scan-assembler "load2r:\n\taddi" } } */
> +/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */
> +/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> +/* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> index 50316284832..3d561124b81 100644
> --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> @@ -36,5 +36,5 @@ load2a (long long a0, long long a1, long long a2, long long a3, long long a4,
> return sub2 (a0, a1, a2, a3, a4, 0, a);
> }
>
> -/* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } } } */
> +/* { dg-final { scan-assembler-not "load1a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */
> /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ \t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" { xfail riscv*-*-* } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> index d985512e2b3..26decf085fb 100644
> --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> @@ -23,5 +23,5 @@ store2z (long long *array)
> array[203] = 0;
> }
>
> -/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
> -/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
> +/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
> +/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
> index 9217922c10d..11e858ed6da 100644
> --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
> @@ -44,11 +44,11 @@ load2r (long long *array)
> return a;
> }
>
> -/* { dg-final { scan-assembler "store1a:\n\taddi" } } */
> +/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> /* The sd insns in store2a are not rewritten because shorten_memrefs currently
> only optimizes lw and sw.
> -/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-* } } } */
> -/* { dg-final { scan-assembler "load1r:\n\taddi" } } */
> +/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */
> +/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> /* The ld insns in load2r are not rewritten because shorten_memrefs currently
> only optimizes lw and sw.
> -/* { dg-final { scan-assembler "load2r:\n\taddi" { xfail riscv*-*-* } } } */
> +/* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
> index c36af6d6a5d..b6539b76aaf 100644
> --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
> @@ -36,5 +36,5 @@ load2a (long long a0, long long a1, long long a2, long long a3, long long a4,
> return sub2 (a0, a1, a2, a3, a4, 0, a);
> }
>
> -/* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } } } */
> +/* { dg-final { scan-assembler-not "load1a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-* } } } */
> /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ \t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
> index 6dfc015cf3a..3ff6956b33e 100644
> --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
> +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
> @@ -23,6 +23,6 @@ load (char *p)
> return a;
> }
>
> -/* { dg-final { scan-assembler "store:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */
> -/* { dg-final { scan-assembler "load:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */
> +/* { dg-final { scan-assembler "store:\n(\t?\\.\[^\n\]*\n)*\taddi\ta\[0-7\],a\[0-7\],1" } } */
> +/* { dg-final { scan-assembler "load:\n(\t?\\.\[^\n\]*\n)*\taddi\ta\[0-7\],a\[0-7\],1" } } */
next prev parent reply other threads:[~2023-02-09 19:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-09 9:48 Andreas Schwab
2023-02-09 19:09 ` Palmer Dabbelt [this message]
2023-02-09 19:19 ` Andrew Pinski
2023-02-13 10:02 ` Andreas Schwab
2023-02-11 1:50 ` Jeff Law
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