From: Richard Sandiford <richard.sandiford@arm.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: gcc-patches@gcc.gnu.org,
Tamar Christina <tamar.christina@arm.com>,
Christoph Muellner <christoph.muellner@vrull.eu>
Subject: Re: [PATCH v2] aarch64: update Ampere-1 core definition
Date: Thu, 06 Oct 2022 11:07:34 +0100 [thread overview]
Message-ID: <mptpmf5i7tl.fsf@arm.com> (raw)
In-Reply-To: <20221006092951.607412-1-philipp.tomsich@vrull.eu> (Philipp Tomsich's message of "Thu, 6 Oct 2022 11:29:51 +0200")
Philipp Tomsich <philipp.tomsich@vrull.eu> writes:
> This brings the extensions detected by -mcpu=native on Ampere-1 systems
> in sync with the defaults generated for -mcpu=ampere1.
>
> Note that some early kernel versions on Ampere1 may misreport the
> presence of PAUTH and PREDRES (i.e., -mcpu=native will add 'nopauth'
> and 'nopredres').
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
> Ampere-1 core entry.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
OK, thanks.
> Ok for backport?
Yeah. I'll try to backport the RCPC change soon -- think it would
be best to get that in first.
Richard
>
> Changes in v2:
> - Removed explicit RCPC, as the feature is now implicitly included
> in the 8.3 feature definition.
>
> gcc/config/aarch64/aarch64-cores.def | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
> index b50628d6b51..e9a4b622be0 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -69,7 +69,7 @@ AARCH64_CORE("thunderxt81", thunderxt81, thunderx, V8A, (CRC, CRYPTO), thu
> AARCH64_CORE("thunderxt83", thunderxt83, thunderx, V8A, (CRC, CRYPTO), thunderx, 0x43, 0x0a3, -1)
>
> /* Ampere Computing ('\xC0') cores. */
> -AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (), ampere1, 0xC0, 0xac3, -1)
> +AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES, SHA3), ampere1, 0xC0, 0xac3, -1)
> /* Do not swap around "emag" and "xgene1",
> this order is required to handle variant correctly. */
> AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), emag, 0x50, 0x000, 3)
next prev parent reply other threads:[~2022-10-06 10:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 9:29 Philipp Tomsich
2022-10-06 10:07 ` Richard Sandiford [this message]
2022-10-06 10:39 ` Philipp Tomsich
2022-10-20 14:35 ` Richard Sandiford
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