* [PATCH] libgcc, aarch64: Allow for BE platforms in heap trampolines.
@ 2024-02-20 10:34 Iain Sandoe
2024-02-20 20:20 ` Richard Sandiford
0 siblings, 1 reply; 2+ messages in thread
From: Iain Sandoe @ 2024-02-20 10:34 UTC (permalink / raw)
To: gcc-patches; +Cc: pinskia
Andrew Pinski pointed out on irc, that the current implementation of the
heap trampoline code fragment would make the instruction byte order follow
memory byte order for BE AArch64, which is not what is required.
This patch revises the initializers so that instruction byte order is
independent of memory byte order.
I have tested this on aarch64-linux-gnu, aarch64-darwin and on a cross to
aarch64_be-linux-gnu (including compile tests on the latter, but I have no
way, at present, to carry out execute tests).
(Note that this patch is applied on top of the one for PR113971).
OK for trunk, or what would be a way forward?
thanks
Iain
--- 8< ---
This arranges that the byte order of the instruction sequences is
independent of the byte order of memory.
libgcc/ChangeLog:
* config/aarch64/heap-trampoline.c
(aarch64_trampoline_insns): Arrange to encode instructions as a
byte array so that the order is independent of memory byte order.
(struct aarch64_trampoline): Likewise.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
---
libgcc/config/aarch64/heap-trampoline.c | 30 ++++++++++++-------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/libgcc/config/aarch64/heap-trampoline.c b/libgcc/config/aarch64/heap-trampoline.c
index 1e3460b1601..885df629da7 100644
--- a/libgcc/config/aarch64/heap-trampoline.c
+++ b/libgcc/config/aarch64/heap-trampoline.c
@@ -30,23 +30,23 @@ void __gcc_nested_func_ptr_created (void *chain, void *func, void *dst);
void __gcc_nested_func_ptr_deleted (void);
#if defined(__linux__)
-static const uint32_t aarch64_trampoline_insns[] = {
- 0xd503245f, /* hint 34 */
- 0x580000b1, /* ldr x17, .+20 */
- 0x580000d2, /* ldr x18, .+24 */
- 0xd61f0220, /* br x17 */
- 0xd5033f9f, /* dsb sy */
- 0xd5033fdf /* isb */
+static const unsigned char aarch64_trampoline_insns[6][4] = {
+ {0x5f, 0x24, 0x03, 0xd5}, /* hint 34 */
+ {0xb1, 0x00, 0x00, 0x58}, /* ldr x17, .+20 */
+ {0xd2, 0x00, 0x00, 0x58}, /* ldr x18, .+24 */
+ {0x20, 0x02, 0x1f, 0xd6}, /* br x17 */
+ {0x9f, 0x3f, 0x03, 0xd5}, /* dsb sy */
+ {0xdf, 0x3f, 0x03, 0xd5} /* isb */
};
#elif __APPLE__
-static const uint32_t aarch64_trampoline_insns[] = {
- 0xd503245f, /* hint 34 */
- 0x580000b1, /* ldr x17, .+20 */
- 0x580000d0, /* ldr x16, .+24 */
- 0xd61f0220, /* br x17 */
- 0xd5033f9f, /* dsb sy */
- 0xd5033fdf /* isb */
+static const unsigned char aarch64_trampoline_insns[6][4] = {
+ {0x5f, 0x24, 0x03, 0xd5}, /* hint 34 */
+ {0xb1, 0x00, 0x00, 0x58}, /* ldr x17, .+20 */
+ {0xd0, 0x00, 0x00, 0x58}, /* ldr x16, .+24 */
+ {0x20, 0x02, 0x1f, 0xd6}, /* br x17 */
+ {0x9f, 0x3f, 0x03, 0xd5}, /* dsb sy */
+ {0xdf, 0x3f, 0x03, 0xd5} /* isb */
};
#else
@@ -54,7 +54,7 @@ static const uint32_t aarch64_trampoline_insns[] = {
#endif
struct aarch64_trampoline {
- uint32_t insns[6];
+ unsigned char insns[6][4];
void *func_ptr;
void *chain_ptr;
};
--
2.39.2 (Apple Git-143)
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] libgcc, aarch64: Allow for BE platforms in heap trampolines.
2024-02-20 10:34 [PATCH] libgcc, aarch64: Allow for BE platforms in heap trampolines Iain Sandoe
@ 2024-02-20 20:20 ` Richard Sandiford
0 siblings, 0 replies; 2+ messages in thread
From: Richard Sandiford @ 2024-02-20 20:20 UTC (permalink / raw)
To: Iain Sandoe; +Cc: gcc-patches, iain, pinskia
Iain Sandoe <iains.gcc@gmail.com> writes:
> Andrew Pinski pointed out on irc, that the current implementation of the
> heap trampoline code fragment would make the instruction byte order follow
> memory byte order for BE AArch64, which is not what is required.
>
> This patch revises the initializers so that instruction byte order is
> independent of memory byte order.
>
> I have tested this on aarch64-linux-gnu, aarch64-darwin and on a cross to
> aarch64_be-linux-gnu (including compile tests on the latter, but I have no
> way, at present, to carry out execute tests).
>
> (Note that this patch is applied on top of the one for PR113971).
>
> OK for trunk, or what would be a way forward?
> thanks
> Iain
>
> --- 8< ---
>
> This arranges that the byte order of the instruction sequences is
> independent of the byte order of memory.
>
> libgcc/ChangeLog:
>
> * config/aarch64/heap-trampoline.c
> (aarch64_trampoline_insns): Arrange to encode instructions as a
> byte array so that the order is independent of memory byte order.
> (struct aarch64_trampoline): Likewise.
>
> Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
OK, thanks.
Richard
> ---
> libgcc/config/aarch64/heap-trampoline.c | 30 ++++++++++++-------------
> 1 file changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/libgcc/config/aarch64/heap-trampoline.c b/libgcc/config/aarch64/heap-trampoline.c
> index 1e3460b1601..885df629da7 100644
> --- a/libgcc/config/aarch64/heap-trampoline.c
> +++ b/libgcc/config/aarch64/heap-trampoline.c
> @@ -30,23 +30,23 @@ void __gcc_nested_func_ptr_created (void *chain, void *func, void *dst);
> void __gcc_nested_func_ptr_deleted (void);
>
> #if defined(__linux__)
> -static const uint32_t aarch64_trampoline_insns[] = {
> - 0xd503245f, /* hint 34 */
> - 0x580000b1, /* ldr x17, .+20 */
> - 0x580000d2, /* ldr x18, .+24 */
> - 0xd61f0220, /* br x17 */
> - 0xd5033f9f, /* dsb sy */
> - 0xd5033fdf /* isb */
> +static const unsigned char aarch64_trampoline_insns[6][4] = {
> + {0x5f, 0x24, 0x03, 0xd5}, /* hint 34 */
> + {0xb1, 0x00, 0x00, 0x58}, /* ldr x17, .+20 */
> + {0xd2, 0x00, 0x00, 0x58}, /* ldr x18, .+24 */
> + {0x20, 0x02, 0x1f, 0xd6}, /* br x17 */
> + {0x9f, 0x3f, 0x03, 0xd5}, /* dsb sy */
> + {0xdf, 0x3f, 0x03, 0xd5} /* isb */
> };
>
> #elif __APPLE__
> -static const uint32_t aarch64_trampoline_insns[] = {
> - 0xd503245f, /* hint 34 */
> - 0x580000b1, /* ldr x17, .+20 */
> - 0x580000d0, /* ldr x16, .+24 */
> - 0xd61f0220, /* br x17 */
> - 0xd5033f9f, /* dsb sy */
> - 0xd5033fdf /* isb */
> +static const unsigned char aarch64_trampoline_insns[6][4] = {
> + {0x5f, 0x24, 0x03, 0xd5}, /* hint 34 */
> + {0xb1, 0x00, 0x00, 0x58}, /* ldr x17, .+20 */
> + {0xd0, 0x00, 0x00, 0x58}, /* ldr x16, .+24 */
> + {0x20, 0x02, 0x1f, 0xd6}, /* br x17 */
> + {0x9f, 0x3f, 0x03, 0xd5}, /* dsb sy */
> + {0xdf, 0x3f, 0x03, 0xd5} /* isb */
> };
>
> #else
> @@ -54,7 +54,7 @@ static const uint32_t aarch64_trampoline_insns[] = {
> #endif
>
> struct aarch64_trampoline {
> - uint32_t insns[6];
> + unsigned char insns[6][4];
> void *func_ptr;
> void *chain_ptr;
> };
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2024-02-20 10:34 [PATCH] libgcc, aarch64: Allow for BE platforms in heap trampolines Iain Sandoe
2024-02-20 20:20 ` Richard Sandiford
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