From: Richard Biener <rguenther@suse.de>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, richard.guenther@gmail.com
Subject: Re: [PATCH] OPTABS: Extend the number of expanding instructions pattern.
Date: Mon, 15 May 2023 12:51:35 +0000 (UTC) [thread overview]
Message-ID: <nycvar.YFH.7.77.849.2305151251290.4723@jbgna.fhfr.qr> (raw)
In-Reply-To: <20230515122235.293830-1-juzhe.zhong@rivai.ai>
On Mon, 15 May 2023, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Hi, Richi.
>
> We (RVV) is going to add a rounding mode operand into floating-point instructions
> which have 11 operands.
>
> Since we are going have intrinsic that is adding rounding mode argument:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
>
> This is the patch that is adding rounding mode operand in RISC-V port:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
> You can see there are 11 operands in these patterns.
>
> Is it Ok for trunk ?
OK.
Richard.
> Thanks
>
> gcc/ChangeLog:
>
> * optabs.cc (maybe_gen_insn): Add case to generate instruction that has 11 operands.
>
> ---
> gcc/optabs.cc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/gcc/optabs.cc b/gcc/optabs.cc
> index c8e39c82d57..a12333c7169 100644
> --- a/gcc/optabs.cc
> +++ b/gcc/optabs.cc
> @@ -8139,6 +8139,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
> ops[3].value, ops[4].value, ops[5].value,
> ops[6].value, ops[7].value, ops[8].value,
> ops[9].value);
> + case 11:
> + return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
> + ops[3].value, ops[4].value, ops[5].value,
> + ops[6].value, ops[7].value, ops[8].value,
> + ops[9].value, ops[10].value);
> }
> gcc_unreachable ();
> }
>
--
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)
next prev parent reply other threads:[~2023-05-15 12:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 12:22 juzhe.zhong
2023-05-15 12:22 ` [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong
2023-05-15 13:43 ` Jeff Law
2023-05-15 12:51 ` Richard Biener [this message]
2023-05-15 14:14 ` [PATCH] OPTABS: Extend the number of expanding instructions pattern Li, Pan2
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