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From: Jeff Law <jeffreyalaw@gmail.com>
To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org
Cc: richard.guenther@gmail.com, rguenther@suse.de
Subject: Re: [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
Date: Mon, 15 May 2023 07:43:16 -0600	[thread overview]
Message-ID: <2d811b78-cffa-165b-5d79-aaee43977326@gmail.com> (raw)
In-Reply-To: <20230515122235.293830-2-juzhe.zhong@rivai.ai>



On 5/15/23 06:22, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> This patch is adding FRM and rounding mode into floating-point ternary instructions.
> This patch should be merged after optabs.cc patch.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add default rounding mode.
>          * config/riscv/vector.md: Add rounding mode operand and FRM_REGNUM.
OK
jeff

  reply	other threads:[~2023-05-15 13:43 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-15 12:22 [PATCH] OPTABS: Extend the number of expanding instructions pattern juzhe.zhong
2023-05-15 12:22 ` [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong
2023-05-15 13:43   ` Jeff Law [this message]
2023-05-15 12:51 ` [PATCH] OPTABS: Extend the number of expanding instructions pattern Richard Biener
2023-05-15 14:14   ` Li, Pan2
  -- strict thread matches above, loose matches on Subject: below --
2023-05-15 12:16 [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong

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