[PATCH][committed][testsuite]: move mla_1 test to aarch64 only [PR109118]

[PATCH][committed][testsuite]: move mla_1 test to aarch64 only [PR109118]

[Tamar Christina]

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Hi All,

I previously made the test generic, but there's no list
of targets that support integer MLA, and so it's not
really feasible for me to make this generic.

As such I've moved it to be AArch64 only.

committed under the obvious rule.

Thanks,
Tamar

gcc/testsuite/ChangeLog:

	PR testsuite/109118
	* gcc.dg/mla_1.c: Moved to...
	* gcc.target/aarch64/sve/mla_3.c: ...here.

--- inline copy of patch -- 
diff --git a/gcc/testsuite/gcc.dg/mla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c
similarity index 78%
rename from gcc/testsuite/gcc.dg/mla_1.c
rename to gcc/testsuite/gcc.target/aarch64/sve/mla_3.c
index 98e5808ee7005e3e5c1b2d5688bfaf267a4d66ce..25e99f7d72a2fd5be0cdf9a8e9d9edddf22c40cb 100644
--- a/gcc/testsuite/gcc.dg/mla_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target vect_int } */
-/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" { target aarch64*-*-* } } */
+/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" } */
 
 unsigned int
 f1 (unsigned int a, unsigned int b, unsigned int c) {
@@ -37,4 +36,4 @@ g3 (vec a, vec b, vec c)
   return a * b + c;
 }
 
-/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" } } */




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diff --git a/gcc/testsuite/gcc.dg/mla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c
similarity index 78%
rename from gcc/testsuite/gcc.dg/mla_1.c
rename to gcc/testsuite/gcc.target/aarch64/sve/mla_3.c
index 98e5808ee7005e3e5c1b2d5688bfaf267a4d66ce..25e99f7d72a2fd5be0cdf9a8e9d9edddf22c40cb 100644
--- a/gcc/testsuite/gcc.dg/mla_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target vect_int } */
-/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" { target aarch64*-*-* } } */
+/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" } */
 
 unsigned int
 f1 (unsigned int a, unsigned int b, unsigned int c) {
@@ -37,4 +36,4 @@ g3 (vec a, vec b, vec c)
   return a * b + c;
 }
 
-/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" } } */