[PATCH] RISC-V: Add VLS to mask vec_extract [PR114668].

[PATCH] RISC-V: Add VLS to mask vec_extract [PR114668].

[Robin Dapp]

Hi,

this adds the missing VLS modes to the mask extract expanders.
I found a dump scan difficult to create reliably so I just
kept the PR's run test case.

Regtested on rv64gcv. 

Regards
 Robin

gcc/ChangeLog:

	PR target/114668

	* config/riscv/autovec.md: Add VLS.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr114668.c: New test.
---
 gcc/config/riscv/autovec.md                   |  4 +--
 .../gcc.target/riscv/rvv/autovec/pr114668.c   | 35 +++++++++++++++++++
 2 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3b32369f68c..aa1ae0fe075 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1427,7 +1427,7 @@ (define_expand "vec_extract<mode><vel>"
 (define_expand "vec_extract<mode>qi"
   [(set (match_operand:QI	  0 "register_operand")
      (vec_select:QI
-       (match_operand:VB	  1 "register_operand")
+       (match_operand:VB_VLS	  1 "register_operand")
        (parallel
 	 [(match_operand	  2 "nonmemory_operand")])))]
   "TARGET_VECTOR"
@@ -1453,7 +1453,7 @@ (define_expand "vec_extract<mode>qi"
 (define_expand "vec_extract<mode>bi"
   [(set (match_operand:QI	  0 "register_operand")
      (vec_select:QI
-       (match_operand:VB	  1 "register_operand")
+       (match_operand:VB_VLS	  1 "register_operand")
        (parallel
 	 [(match_operand	  2 "nonmemory_operand")])))]
   "TARGET_VECTOR"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c
new file mode 100644
index 00000000000..3a13c3c0012
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -O3 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d  } } */
+
+char a;
+int b;
+short e[14];
+char f[4][12544];
+_Bool c[4][5];
+
+__attribute__ ((noipa))
+void foo (int a)
+{
+  if (a != 1)
+    __builtin_abort ();
+}
+
+int main ()
+{
+  for (int i = 0; i < 4; ++i)
+    for (int l = 0; l < 15; ++l)
+      for (int m = 0; m < 15; ++m)
+	f[i][l * m] = 3;
+  for (int j = 0; j < 4; j += 1)
+    for (int k = 3; k < 13; k += 3)
+      for (_Bool l = 0; l < 1; l = 1)
+	for (int m = 0; m < 4; m += 1)
+	  {
+	    a = 0;
+	    b -= e[k];
+	    c[j][m] = f[j][6];
+	  }
+  for (long i = 2; i < 4; ++i)
+    foo (c[3][3]);
+}
-- 
2.44.0

Re: [PATCH] RISC-V: Add VLS to mask vec_extract [PR114668].

[=?gb18030?B?1tO+09Xc?=]

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lgtm








 ----------Reply to Message----------
 On Mon, Apr 15, 2024 20:43 PM Robin Dapp<rdapp.gcc@gmail.com&gt; wrote:

  Hi,

this adds the missing VLS modes to the mask extract expanders.
I found a dump scan difficult to create reliably so I just
kept the PR's run test case.

Regtested on rv64gcv. 

Regards
&nbsp;Robin

gcc/ChangeLog:

PR target/114668

* config/riscv/autovec.md: Add VLS.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr114668.c: New test.
---
&nbsp;gcc/config/riscv/autovec.md&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp; 4 +--
&nbsp;.../gcc.target/riscv/rvv/autovec/pr114668.c&nbsp;&nbsp; | 35 +++++++++++++++++++
&nbsp;2 files changed, 37 insertions(+), 2 deletions(-)
&nbsp;create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3b32369f68c..aa1ae0fe075 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1427,7 +1427,7 @@ (define_expand "vec_extract<mode&gt;<vel&gt;"
&nbsp;(define_expand "vec_extract<mode&gt;qi"
&nbsp;&nbsp; [(set (match_operand:QI&nbsp; 0 "register_operand")
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_select:QI
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:VB&nbsp; 1 "register_operand")
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:VB_VLS&nbsp; 1 "register_operand")
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (parallel
&nbsp; [(match_operand&nbsp; 2 "nonmemory_operand")])))]
&nbsp;&nbsp; "TARGET_VECTOR"
@@ -1453,7 +1453,7 @@ (define_expand "vec_extract<mode&gt;qi"
&nbsp;(define_expand "vec_extract<mode&gt;bi"
&nbsp;&nbsp; [(set (match_operand:QI&nbsp; 0 "register_operand")
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (vec_select:QI
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:VB&nbsp; 1 "register_operand")
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:VB_VLS&nbsp; 1 "register_operand")
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (parallel
&nbsp; [(match_operand&nbsp; 2 "nonmemory_operand")])))]
&nbsp;&nbsp; "TARGET_VECTOR"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c
new file mode 100644
index 00000000000..3a13c3c0012
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -O3 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d&nbsp; } } */
+
+char a;
+int b;
+short e[14];
+char f[4][12544];
+_Bool c[4][5];
+
+__attribute__ ((noipa))
+void foo (int a)
+{
+&nbsp; if (a != 1)
+&nbsp;&nbsp;&nbsp; __builtin_abort ();
+}
+
+int main ()
+{
+&nbsp; for (int i = 0; i < 4; ++i)
+&nbsp;&nbsp;&nbsp; for (int l = 0; l < 15; ++l)
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; for (int m = 0; m < 15; ++m)
+f[i][l * m] = 3;
+&nbsp; for (int j = 0; j < 4; j += 1)
+&nbsp;&nbsp;&nbsp; for (int k = 3; k < 13; k += 3)
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; for (_Bool l = 0; l < 1; l = 1)
+for (int m = 0; m < 4; m += 1)
+&nbsp; {
+&nbsp;&nbsp;&nbsp; a = 0;
+&nbsp;&nbsp;&nbsp; b -= e[k];
+&nbsp;&nbsp;&nbsp; c[j][m] = f[j][6];
+&nbsp; }
+&nbsp; for (long i = 2; i < 4; ++i)
+&nbsp;&nbsp;&nbsp; foo (c[3][3]);
+}
-- 
2.44.0