public inbox for gcc-prs@sourceware.org
help / color / mirror / Atom feed
* target/7282: powerpc64 SImode in FPR
@ 2002-07-12  0:16 Alan Modra
  0 siblings, 0 replies; 4+ messages in thread
From: Alan Modra @ 2002-07-12  0:16 UTC (permalink / raw)
  To: gcc-gnats


>Number:         7282
>Category:       target
>Synopsis:       unrecognizable insn
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    unassigned
>State:          open
>Class:          ice-on-legal-code
>Submitter-Id:   net
>Arrival-Date:   Fri Jul 12 00:16:00 PDT 2002
>Closed-Date:
>Last-Modified:
>Originator:     Alan Modra
>Release:        3.1.1 20020711 (prerelease)
>Organization:
IBM
>Environment:
configured with: /src/gcc-3.1/configure --prefix=/usr/local --build=i686-linux --host=i686-linux --target=powerpc64-linux --disable-nls --enable-languages=c
>Description:
stuart.c: In function `testcase':
stuart.c:170: unrecognizable insn:
(insn 789 199 203 (set (subreg:SI (reg:DI 38 f6) 4)
        (mem:SI (plus:DI (reg/f:DI 1 r1)
                (const_int 116 [0x74])) [15 S4 A8])) -1 (nil)
    (nil))
stuart.c:170: Internal compiler error in extract_insn, at recog.c:2148
>How-To-Repeat:
	-O2 on attached testcase
>Fix:
	Not yet

--HcAYCG3uE/tztfnV
Content-Type: application/x-gunzip
Content-Disposition: attachment; filename="stuart.i.gz"
Content-Transfer-Encoding: base64

H4sICKl+Lj0CA3N0dWFydC5pAO0aaW/bOPa7fwXRAgvbuSzJcRKoHaBFu8gGi7maL4MgEBSJ
dtTYkkdHYu0g/33e4yVKopxKaXe/rIEo1rsvko+k3xKLvMnywk/z4+DN6C2+vrsronV+FMU/
SUCQbDZ+HJJ1FFMJbDCtgmAxP4HnSRQH6yKkJ+toE+XZ8f0bQDtAZGs8xOZcJ0WWnqyTwF+f
bJMnmm5ByBFoKXZKTFZmJ3m5pbqkRX9O55sVLqmfF2lN37nTm9Pp5WAQ0mVN4by3QptxOpb9
A01dxcUJ5PBOM9WxnIGm2mf9s4ic8PlWe++gAFvFczGA1ekq8iwPIXWa9NkLZM4IhcILWSfx
ihRxFq1iGpIozkkW/Yd6uYtRnQ0wkgdHileSg3s/JZ5XePjFbeOz+yTNGQH7ZqBA2xAP/w1Y
5gei8Ys7Gnke3eUUsEnsecRMzh5S7J+FH6LbZsYmvaR+S+bDMikF18MDws89k3syfE2CWvS4
afC0FkYhOlXRIquFGZ6O7e1JgyLoCFhHnOG5mHeHuTs/ilFZJJNApvDND8O0gZUpha8hfdR9
EVXExIZmxKqNEBUWxYmZZZOE1IyJoRQedJTmWLJc1pmU0esGitNv64ZxYCbHrMHeFFbAJkrp
QCQPa9tqrqgqjzwtgnxEyF/wR4TiR399Y9+6AHmGt2UmeBrmhTI7EsyqGdIWNBFaYPJoQ/cV
YEaDJA6zDu7sJfzT3fqB26q5LopaaK8PAB2rpIshYNIQwHzwYIoGQ5gDhVpTYVUL+UDLOo9x
XEfbQNaI2S7wW1ZLN0UQ5x1VyZFiKJrqbZmZ+LWakwR7ZSyj9X4ZnMAkQxHBSG3j+ajiA6+J
1avPy2A291Ovc62RdEVF2MwYPLd52pE0UYdQC2say2z0aim2+X1K/bDZWTjDJTj9DMiCexpW
mhfnA1idEZ9YMBYI87Z+6m8a04zApFGSRnnJphtceu35cFd5myJ1C6y39LMch+cItevTRQ59
Y4aKxfs2ipEOsvZcG2hNgSHNgtQT0Gkd7NZHuYqDJPJzKJ6MmSLmUZr7wT3aQjVTMDbbZB0F
LDCmaCoqfKk4o/ieQjwZSpeXbJl4PkvgWgjbpRDfNCIw5IFN3hnNEfyYRCHO6ApRk8CgXMIz
qbmXG6LHPO7KDE6gHg89aYSZoZ78KI+wA6wU4UzdrUiEtthsyiZTZaFx9EpSNTHvU7DxYNtB
00c91BvQUsS50ZONlzzFNNWJH6I4dPeHZiNCU/mxKXK6e8l7RsTFNzgNSdJdT+JA7BWs+ew1
8073HCtVcS2nQ7ckuEccvNPTlxfWuzS3MWrfQlr7F9lQNTYuarWTO5bWWiu3GIa1rdqtVEje
fJGqBzOserKlbDQ90NAS0dbCLG4NOdaoxLFem4iOu66JNdVkZTKQN89E9tB1pOifieqjGzlh
YotKrIbjfgu335KLi9c5xzorsjV5wDAmhGjOSaa3XXrAeBNMWl2y6o+J6pMbrGzmIWL+gdHh
2D/ySAq702q1P5v1YtKjyFt7Ijv8t+TcHixLddNE66sh0fNXWZcK81IZWGfY3IHz4vBjwpcP
eqz52asntfaUW9RnJMM+o9h3SFOwiQ6Mu5i9ZrShKH7cAUnBdSi6gxXJ88h4LOYL+Op5v/3L
8yaTidvkw8ONvYyXHYxij9fN+KWDEbcTexk/ScaOhqLwhvjbFtHf9baM/lFoy+gRED2UKV1F
Wc7G4D7mpyQNBTtsBawfOvXROIz8WDtvPuvJ1nNn1dJ33lOfONy2nKHTQ597g4yuaZDrp/ED
WPvuPZs67QE6+7nK9UYr2PIM225XvE7zAC9aQaUnmyho9g+NYzfTGQQewo2tGeyGT8j4nEzZ
vitZknGLGAaLOqzjxoiD/tPBwdMbHSGRVKJ7HWrU+wtrtui5hIt9EQKyLQ1UzKqG4xG2q4HL
gCp+AIwFlB0qzAfHot99UM3ZhdOfs+Yw1MB+f2tHoogpKqergxAhyrEbwthq0CFO4opaFM8G
V5RWUJrFtQPdrpPLJexa/exBnp+aBhH/cBcEOfuWeRjcG9MwUoRs9IzY+AEIO/loduRSpLIE
WtHTQbOh+OAtSRrzizmGJWNxqQA2Hwo78OQlpeBlxI5+cL+MWOZm42NkeEqjnPbioLuAbvMu
lno1NVgRmhT5hLAe0TofFh1c3Bb/lcWtzDZ+kCb6Eat1MXQ7YDuz1+1A5eE6qU7Z6wWojt+J
fhLfoJHH60Q/acefNAzqonAFGfizijyEatYie9aTrWfX8ITHNvovHHqqs3srTPjRae+b/6bO
+UXvyJgvkYvOO2Zte6cuh7t3ePLqa98+Ul3awgq3GGy/bj0gvTX1s8YtuLJc4et32zWUsLy1
figCeS806vwhQ2G2oyOUJota8TTaZo6pbiWsL9Z3i+xSOmQOzrLlRQtdvzNtoaXN1mz+HcvZ
YHdH4JbdeWgTdvwAok2ovLJng73SQ9V9aVjTLcjweOr0u+jd+LuXPRZEMCPVp/zKWhoXG9Y9
fvzw+7X38+cPv3/+ck3ek9mhhF3+8u9PfwDEUpCPH37+9BtA7DrEBpAzeibYPnir5O4uYRW/
0H/4x66eciAI/IySsbjUmN4Fycc0ye8P+Wu0Wq2pDth9yUFAJt5K8Sa5syikgKvX2jTM8k9+
7rfgU/xJ4ocwTCU/EF59gYYnpFx+lgbqvfKFsOdoom5idn8U2/yQ7IIkTQ/J9eUhuZIXQLsv
aXBISnhKCDcZAsRsvZndKsQ/ozjK7hXGUpjw+lJB7Qp6pYAOAza8A+N/uct/zVMDDhzdh/tY
LD/H6sbrq4vN8zJJyfgrqOQOuOQrefdeGg1vBwcTtfsIk+JuTcluOYOoLC182PhwXB1dIrpE
dInosoEOABsAMgBc4BwSaElnNYJwdwh/no1P9nA88a8uKCwBWjJcyR6crmzS4S8CKJb3MWwl
FqenzuLYVbfZGViTgTUZsGZgzYOGmgPoFP4W8HfGgiUqjhy812oKOVipgA5Z5jdfWepY6QC4
KneBYJkXNS9AVyoHEhLBbocL/olLmhDYc+UwiTCdKtnAOK4lezpRhkK/MuXWCRZeAy+zoD6X
b81YiTzglOGSB/KO2PAPykIUBQ/W9aUFBNeXrga7QtCVhDTLkRteOXGAsZfc4DkfjuT9e31K
qpSCMzv0AhX/g4zHFnn3jliLCTki1mSC+0VMuwv1gFRXLxBBuaF/x6cAC3cuq6sKUCIFvoNK
iWevpcI6Hsd7NqOwXV6PjIjDSpvTOTiJHs8YGVBwQg1YMiCMMSbPBlO59CMmHTEWwyDTEbGF
yTbEzzqeIRqV2kKBZHcALdkdwY446TEgXBdHLjOYcZVCaYlcJVda1pSWSmmpK1XsTKlgdwS7
phQCInL5TOgaFosflNpvS1w7bc2kqZhWKVMey4TJZB2oBKHSKmV6PrR06Wz82UxUPUUyPQcq
JehMlSQ9A1qCdDb+bKZGT8popPLBZgBwG8cprA7jah7BaAsETIr2RLD8pZ1DYBpxwqwmB/xc
ceCVq6khsDhgSrPZFMN5ADPzFGMHX+wpRgq+OPDFmeiSAovxzCXPqeRZSJ4zwaMz2YxJrqU3
81vJrkDWLedvHalUJLNbqUuBFrctAxXSMOuOx6p3nFR0B1qLUvfVedFshxnwstl222yrHqP/
T7DfdYLFRgdDFcymJctZYE1LVj2BPS1ZPgIHvkDx/A9mYj3vvEbQVryl4A2aXs9om15NLgzU
Goh3s4reriHnSO/UQItbTcHzqPr/PHoe/Q0pP7DPjzQAAA==

--HcAYCG3uE/tztfnV--
>Release-Note:
>Audit-Trail:
>Unformatted:
 --HcAYCG3uE/tztfnV
 Content-Type: text/plain; charset=us-ascii
 Content-Disposition: inline
 


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: target/7282: powerpc64 SImode in FPR
@ 2002-07-13 22:46 Alan Modra
  0 siblings, 0 replies; 4+ messages in thread
From: Alan Modra @ 2002-07-13 22:46 UTC (permalink / raw)
  To: nobody; +Cc: gcc-prs

The following reply was made to PR target/7282; it has been noted by GNATS.

From: Alan Modra <amodra@bigpond.net.au>
To: David Edelsohn <dje@watson.ibm.com>
Cc: gcc-gnats@gcc.gnu.org, gcc-patches@gcc.gnu.org
Subject: Re: target/7282: powerpc64 SImode in FPR
Date: Sun, 14 Jul 2002 15:15:21 +0930

 On Sat, Jul 13, 2002 at 10:18:54AM -0400, David Edelsohn wrote:
 > 	This looks okay except for
 > 
 > +  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 > +	(float:DF (match_operand:SI 1 "gpc_reg_operand" "*f")))
 > +   (clobber (match_operand:DI 2 "memory_operand" "=o"))
 > +   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
 > +   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
 > 
 > The input SImode operand should have constraint "r", not "*f".  The whole
 > point of this pattern is to move the SImode operand from the GPR to the
 > FPR because GCC sometimes gets confused when asked to do this itself.
 > SImode is not allowed in FPRs, so the "*f" constraint is contradictory.
 
 Revised patch follows, incorporating your floatunssidf2 suggestion too.
 
 	PR target/7282
 	* config/rs6000/rs6000.md (floatsidf2): Enable for POWERPC64.
 	(floatunssidf2): Likewise.
 	(floatsidf_ppc64): New insn_and_split.
 	(floatunssidf_ppc64): Likewise.
 
 -- 
 Alan Modra
 IBM OzLabs - Linux Technology Centre
 
 Index: gcc/config/rs6000/rs6000.md
 ===================================================================
 RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
 retrieving revision 1.192
 diff -u -p -r1.192 rs6000.md
 --- gcc/config/rs6000/rs6000.md	3 Jul 2002 14:41:22 -0000	1.192
 +++ gcc/config/rs6000/rs6000.md	14 Jul 2002 05:38:17 -0000
 @@ -5350,9 +5350,18 @@
  	      (clobber (match_dup 4))
  	      (clobber (match_dup 5))
  	      (clobber (match_dup 6))])]
 -  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "TARGET_HARD_FLOAT"
    "
  {
 +  if (TARGET_POWERPC64)
 +    {
 +      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
 +      rtx t1 = gen_reg_rtx (DImode);
 +      rtx t2 = gen_reg_rtx (DImode);
 +      emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
 +      DONE;
 +    }
 +
    operands[2] = force_reg (SImode, GEN_INT (0x43300000));
    operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
    operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
 @@ -5417,9 +5426,19 @@
  	      (use (match_dup 3))
  	      (clobber (match_dup 4))
  	      (clobber (match_dup 5))])]
 -  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "TARGET_HARD_FLOAT"
    "
  {
 +  if (TARGET_POWERPC64)
 +    {
 +      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
 +      rtx t1 = gen_reg_rtx (DImode);
 +      rtx t2 = gen_reg_rtx (DImode);
 +      emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
 +					 t1, t2));
 +      DONE;
 +    }
 +
    operands[2] = force_reg (SImode, GEN_INT (0x43300000));
    operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
    operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
 @@ -5533,6 +5552,38 @@
  	(float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
    "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
    "fcfid %0,%1"
 +  [(set_attr "type" "fp")])
 +
 +(define_insn_and_split "floatsidf_ppc64"
 +  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 +	(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
 +   (clobber (match_operand:DI 2 "memory_operand" "=o"))
 +   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
 +   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
 +  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "#"
 +  ""
 +  [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
 +   (set (match_dup 2) (match_dup 3))
 +   (set (match_dup 4) (match_dup 2))
 +   (set (match_dup 0) (float:DF (match_dup 4)))]
 +  ""
 +  [(set_attr "type" "fp")])
 +
 +(define_insn_and_split "floatunssidf_ppc64"
 +  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 +	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
 +   (clobber (match_operand:DI 2 "memory_operand" "=o"))
 +   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
 +   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
 +  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "#"
 +  ""
 +  [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
 +   (set (match_dup 2) (match_dup 3))
 +   (set (match_dup 4) (match_dup 2))
 +   (set (match_dup 0) (float:DF (match_dup 4)))]
 +  ""
    [(set_attr "type" "fp")])
  
  (define_insn "fix_truncdfdi2"


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: target/7282: powerpc64 SImode in FPR
@ 2002-07-13  7:26 David Edelsohn
  0 siblings, 0 replies; 4+ messages in thread
From: David Edelsohn @ 2002-07-13  7:26 UTC (permalink / raw)
  To: nobody; +Cc: gcc-prs

The following reply was made to PR target/7282; it has been noted by GNATS.

From: David Edelsohn <dje@watson.ibm.com>
To: gcc-gnats@gcc.gnu.org, gcc-patches@gcc.gnu.org
Cc:  
Subject: Re: target/7282: powerpc64 SImode in FPR 
Date: Sat, 13 Jul 2002 10:18:54 -0400

 	This looks okay except for
 
 +  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 +	(float:DF (match_operand:SI 1 "gpc_reg_operand" "*f")))
 +   (clobber (match_operand:DI 2 "memory_operand" "=o"))
 +   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
 +   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
 
 The input SImode operand should have constraint "r", not "*f".  The whole
 point of this pattern is to move the SImode operand from the GPR to the
 FPR because GCC sometimes gets confused when asked to do this itself.
 SImode is not allowed in FPRs, so the "*f" constraint is contradictory.
 
 David


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: target/7282: powerpc64 SImode in FPR
@ 2002-07-13  4:36 Alan Modra
  0 siblings, 0 replies; 4+ messages in thread
From: Alan Modra @ 2002-07-13  4:36 UTC (permalink / raw)
  To: nobody; +Cc: gcc-prs

The following reply was made to PR target/7282; it has been noted by GNATS.

From: Alan Modra <amodra@bigpond.net.au>
To: gcc-gnats@gcc.gnu.org
Cc: gcc-patches@gcc.gnu.org, David Edelsohn <dje@watson.ibm.com>
Subject: Re: target/7282: powerpc64 SImode in FPR
Date: Sat, 13 Jul 2002 21:05:15 +0930

 This cures the ICE.  Thanks to dje for putting me on the right track.
 
 gcc/ChangeLog
 	PR 7282
 	* config/rs6000/rs6000.md (floatsidf2): Enable for POWERPC64.
 	(floatsidf_ppc64): New insn_and_split.
 
 Checked with gcc-3.1 i686-linux -> powerpc64-linux cross-compiler.
 Bootstrapping and regresssion testing powerpc-linux mainline just to
 be sure.
 
 -- 
 Alan Modra
 IBM OzLabs - Linux Technology Centre
 
 diff -up gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.md gcc-ppc64-31/gcc/config/rs6000/rs6000.md
 --- gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.md	2002-07-04 19:40:32.000000000 +0930
 +++ gcc-ppc64-31/gcc/config/rs6000/rs6000.md	2002-07-13 20:26:05.000000000 +0930
 @@ -5271,9 +5428,18 @@
  	      (clobber (match_dup 4))
  	      (clobber (match_dup 5))
  	      (clobber (match_dup 6))])]
 -  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "TARGET_HARD_FLOAT"
    "
  {
 +  if (TARGET_POWERPC64)
 +    {
 +      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
 +      rtx t1 = gen_reg_rtx (DImode);
 +      rtx t2 = gen_reg_rtx (DImode);
 +      emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
 +      DONE;
 +    }
 +
    operands[2] = force_reg (SImode, GEN_INT (0x43300000));
    operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
    operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
 @@ -5456,6 +5622,22 @@
    "fcfid %0,%1"
    [(set_attr "type" "fp")])
  
 +(define_insn_and_split "floatsidf_ppc64"
 +  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 +	(float:DF (match_operand:SI 1 "gpc_reg_operand" "*f")))
 +   (clobber (match_operand:DI 2 "memory_operand" "=o"))
 +   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
 +   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
 +  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "#"
 +  ""
 +  [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
 +   (set (match_dup 2) (match_dup 3))
 +   (set (match_dup 4) (match_dup 2))
 +   (set (match_dup 0) (float:DF (match_dup 4)))]
 +  ""
 +  [(set_attr "type" "fp")])
 +
  (define_insn "fix_truncdfdi2"
    [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
  	(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2002-07-14  5:46 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2002-07-12  0:16 target/7282: powerpc64 SImode in FPR Alan Modra
2002-07-13  4:36 Alan Modra
2002-07-13  7:26 David Edelsohn
2002-07-13 22:46 Alan Modra

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).