(no subject)

(no subject)

[Eliot Dresselhaus]

Here is a patch which makes Haifa the default scheduler for alpha-*-* targets and
changes insn timings to reflect this.

This seems generate much better floating point code than the old scheduler and
seems to bootstrap.

I'd appreciate any feedback on these diffs from alpha hackers.  Thanks.

Fri Aug 22 17:36:47 1997  Eliot Dresselhaus  <eliot@sirius.com>

	* configure.in (alpha* targets): default to Haifa scheduler.
	* alpha.md (function units): Use real clock counts for Haifa scheduler.
	* alpha.c (alpha_adjust_cost): Likewise.
	* alpha.h (ISSUE_RATE): Define.

*** configure.in.old	Fri Aug 22 14:18:14 1997
--- configure.in	Fri Aug 22 14:26:26 1997
***************
*** 264,269 ****
--- 264,272 ----
  		use_collect2=yes
  		;;
  	alpha*-*-linux-gnuecoff*)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		tm_file="${tm_file} alpha/linux.h"
  		xm_file="${xm_file} alpha/xm-linux.h"
  		target_cpu_default="MASK_GAS"
***************
*** 273,278 ****
--- 276,284 ----
  		gas=yes gnu_ld=yes
  		;;
  	alpha*-*-linux-gnu*)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		tm_file="${tm_file} alpha/linux.h alpha/elf.h"
  		xm_file="${xm_file} alpha/xm-linux.h"
  		target_cpu_default="MASK_GAS"
***************
*** 287,292 ****
--- 293,301 ----
   		fi
  		;;
  	alpha*-dec-osf[[456789]]*)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		if [[ x$stabs = xyes ]]
  		then
  			tm_file="${tm_file} dbx.h"
***************
*** 305,310 ****
--- 314,322 ----
  		esac
  		;;
  	alpha*-dec-osf[[23]]*)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		tm_file="${tm_file} alpha/osf2or3.h"
  		if [[ x$stabs = xyes ]]
  		then
***************
*** 317,322 ****
--- 329,337 ----
  		use_collect2=yes
  		;;
  	alpha*-dec-osf1.2)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		tm_file="${tm_file} alpha/osf12.h"
  		if [[ x$stabs = xyes ]]
  		then
***************
*** 329,334 ****
--- 344,352 ----
  		use_collect2=yes
  		;;
  	alpha*-*-osf*)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		if [[ x$stabs = xyes ]]
  		then
  			tm_file="${tm_file} dbx.h"
***************
*** 340,345 ****
--- 358,366 ----
  		use_collect2=yes
  		;;
  	alpha*-*-winnt3*)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		tm_file="${tm_file} alpha/win-nt.h"
  		target_cpu_default=MASK_WINDOWS_NT
  		xm_file="${xm_file} config/winnt/xm-winnt.h alpha/xm-winnt.h"
***************
*** 357,362 ****
--- 378,386 ----
  		fi
  		;;
  	alpha*-dec-vms*)
+ 		if [[ x$enable_haifa != xno ]]; then
+ 			enable_haifa=yes
+ 		fi
  		tm_file=alpha/vms.h
  		xm_file="${xm_file} alpha/xm-vms.h"
  		tmake_file=alpha/t-vms
*** config/alpha/alpha.c.old	Sun Aug 17 13:42:19 1997
--- config/alpha/alpha.c	Fri Aug 22 14:22:24 1997
***************
*** 1198,1208 ****
        case TYPE_IMULL:
        case TYPE_IMULQ:
  	/* In these cases, we save one cycle.  */
! 	return cost - 2;
  
        default:
  	/* In all other cases, we save two cycles.  */
! 	return MAX (0, cost - 4);
        }
  
    /* Another case that needs adjustment is an arithmetic or logical
--- 1198,1208 ----
        case TYPE_IMULL:
        case TYPE_IMULQ:
  	/* In these cases, we save one cycle.  */
! 	return cost - 1;
  
        default:
  	/* In all other cases, we save two cycles.  */
! 	return MAX (0, cost - 2);
        }
  
    /* Another case that needs adjustment is an arithmetic or logical
***************
*** 1220,1226 ****
  	return cost;
  
        default:
! 	return 2;
        }
  
    /* The final case is when a compare feeds into an integer branch.  The cost
--- 1220,1226 ----
  	return cost;
  
        default:
! 	return 1;
        }
  
    /* The final case is when a compare feeds into an integer branch.  The cost
***************
*** 1230,1236 ****
        && get_attr_type (dep_insn) == TYPE_ICMP
        && recog_memoized (insn) >= 0
        && get_attr_type (insn) == TYPE_IBR)
!     return 2;
  
    /* Otherwise, return the default cost. */
  
--- 1230,1236 ----
        && get_attr_type (dep_insn) == TYPE_ICMP
        && recog_memoized (insn) >= 0
        && get_attr_type (insn) == TYPE_IBR)
!     return 1;
  
    /* Otherwise, return the default cost. */
  
*** config/alpha/alpha.h.old	Sun Aug 17 13:41:13 1997
--- config/alpha/alpha.h	Fri Aug 22 14:39:37 1997
***************
*** 1594,1599 ****
--- 1594,1602 ----
     our own exit function.  */
  #define HAVE_ATEXIT
  
+ /* The ev4 are dual issue; ev5 cpus are quad issue. */
+ #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
+ 
  /* Compute the cost of computing a constant rtl expression RTX
     whose rtx-code is CODE.  The body of this macro is a portion
     of a switch statement.  If the code is computed here,
*** config/alpha/alpha.md.old	Sun Aug 17 13:40:59 1997
--- config/alpha/alpha.md	Fri Aug 22 15:07:59 1997
***************
*** 45,66 ****
  ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
  ;; used for FP operations.
  ;;
- ;; We assume that we have been successful in getting double issues and
- ;; hence multiply all costs by two insns per cycle.  The minimum time in
- ;; a function unit is 2 cycle, which will tend to produce the double
- ;; issues.
  
  ;; Memory delivers its result in three cycles.
  (define_function_unit "ev4_abox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "ld,st"))
!   6 2)
  
  ;; Branches have no delay cost, but do tie up the unit for two cycles.
  (define_function_unit "ev4_bbox" 1 1
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "ibr,fbr,jsr"))
!   4 4)
  
  ;; Arithmetic insns are normally have their results available after two
  ;; cycles.  There are a number of exceptions.  They are encoded in
--- 45,62 ----
  ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
  ;; used for FP operations.
  ;;
  
  ;; Memory delivers its result in three cycles.
  (define_function_unit "ev4_abox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "ld,st"))
!   3 1)
  
  ;; Branches have no delay cost, but do tie up the unit for two cycles.
  (define_function_unit "ev4_bbox" 1 1
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "ibr,fbr,jsr"))
!   2 2)
  
  ;; Arithmetic insns are normally have their results available after two
  ;; cycles.  There are a number of exceptions.  They are encoded in
***************
*** 69,75 ****
  (define_function_unit "ev4_ebox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "iadd,ilog,ldsym,shift,cmov,icmp"))
!   4 2)
  
  ;; These really don't take up the integer pipeline, but they do occupy
  ;; IBOX1; we approximate here.
--- 65,71 ----
  (define_function_unit "ev4_ebox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "iadd,ilog,ldsym,shift,cmov,icmp"))
!   2 1)
  
  ;; These really don't take up the integer pipeline, but they do occupy
  ;; IBOX1; we approximate here.
***************
*** 77,211 ****
  (define_function_unit "ev4_ebox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imull"))
!   42 2)
  
  (define_function_unit "ev4_ebox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imulq"))
!   46 2)
  
  (define_function_unit "ev4_imult" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imull"))
!   42 38)
  
  (define_function_unit "ev4_imult" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imulq"))
!   46 42)
  
  (define_function_unit "ev4_fbox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fadd,fmul,fcpys"))
!   12 2)
  
  (define_function_unit "ev4_fbox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivs"))
!   68 0)
  
  (define_function_unit "ev4_fbox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivt"))
!   126 0)
  
  (define_function_unit "ev4_divider" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivs"))
!   68 60)
  
  (define_function_unit "ev4_divider" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivt"))
!   126 118)
  \f
! ;; EV5 scheduling.  EV5 can issue 4 insns per clock.
! ;; Multiply all costs by 4.
  
  ;; EV5 has two integer units.
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "iadd,ilog,icmp,ldsym"))
!   4 4)
  
  ;; Memory takes at least 2 clocks.
  ;; Conditional moves always take 2 ticks.
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "ld,cmov"))
!   8 4)
  
  ;; Loads can dual issue.  Store cannot; nor can loads + stores.
  ;; Model this with a mythical load/store unit.
  (define_function_unit "ev5_ldst" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "ld"))
!   8 4 [(eq_attr "type" "st")])
  
  (define_function_unit "ev5_ldst" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "st"))
!   4 4)
  
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imull"))
!   32 4)
  
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imulq"))
!   48 4)
  
  ;; Multiplies also use the integer multiplier.
  (define_function_unit "ev5_imult" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imull"))
!   16 8)
  
  (define_function_unit "ev5_imult" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imulq"))
!   48 32)
  
  ;; There is only 1 shifter/zapper.
  (define_function_unit "ev5_shift" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "shift"))
!   4 4)
  
  ;; We pretend EV5 has symmetrical 2 fpus,
  ;; even though cpys is the only insn that can issue on either unit.
  (define_function_unit "ev5_fpu" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fadd,fmul,fcpys"))
!   16 4)
    
  ;; Multiplies (resp. adds) also use the fmul (resp. fadd) units.
  (define_function_unit "ev5_fpmul" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fmul"))
!   16 4)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fadd"))
!   16 4)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fbr"))
!   4 4)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fdivs"))
!   60 4)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fdivt"))
!   88 4)
  \f
  ;; First define the arithmetic insns.  Note that the 32-bit forms also
  ;; sign-extend.
--- 73,206 ----
  (define_function_unit "ev4_ebox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imull"))
!   21 1)
  
  (define_function_unit "ev4_ebox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imulq"))
!   23 1)
  
  (define_function_unit "ev4_imult" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imull"))
!   21 19)
  
  (define_function_unit "ev4_imult" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "imulq"))
!   23 21)
  
  (define_function_unit "ev4_fbox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fadd,fmul,fcpys"))
!   6 1)
  
  (define_function_unit "ev4_fbox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivs"))
!   34 0)
  
  (define_function_unit "ev4_fbox" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivt"))
!   63 0)
  
  (define_function_unit "ev4_divider" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivs"))
!   34 30)
  
  (define_function_unit "ev4_divider" 1 0
    (and (eq_attr "cpu" "ev4")
         (eq_attr "type" "fdivt"))
!   64 59)
  \f
! ;; EV5 scheduling.
  
  ;; EV5 has two integer units.
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "iadd,ilog,icmp,ldsym"))
!   1 1)
  
  ;; Memory takes at least 2 clocks.
  ;; Conditional moves always take 2 ticks.
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "ld,cmov"))
!   2 1)
  
  ;; Loads can dual issue.  Store cannot; nor can loads + stores.
  ;; Model this with a mythical load/store unit.
  (define_function_unit "ev5_ldst" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "ld"))
!   2 1 [(eq_attr "type" "st")])
  
  (define_function_unit "ev5_ldst" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "st"))
!   2 2)
  
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imull"))
!   8 1)
  
  (define_function_unit "ev5_ebox" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imulq"))
!   12 1)
  
  ;; Multiplies also use the integer multiplier.
  (define_function_unit "ev5_imult" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imull"))
!   8 4)
  
  (define_function_unit "ev5_imult" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "imulq"))
!   12 8)
  
  ;; There is only 1 shifter/zapper.
  (define_function_unit "ev5_shift" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "shift"))
!   1 1)
  
  ;; We pretend EV5 has symmetrical 2 fpus,
  ;; even though cpys is the only insn that can issue on either unit.
  (define_function_unit "ev5_fpu" 2 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fadd,fmul,fcpys"))
!   4 1)
    
  ;; Multiplies (resp. adds) also use the fmul (resp. fadd) units.
  (define_function_unit "ev5_fpmul" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fmul"))
!   4 1)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fadd"))
!   4 1)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fbr"))
!   1 1)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fdivs"))
!   15 1)
  
  (define_function_unit "ev5_fpadd" 1 0
    (and (eq_attr "cpu" "ev5")
         (eq_attr "type" "fdivt"))
!   22 1)
  \f
  ;; First define the arithmetic insns.  Note that the 32-bit forms also
  ;; sign-extend.

Re:

[Jeffrey A Law]

  In message <199708262120.OAA26639@wally.edc.com>you write:
  > Here is a patch which makes Haifa the default scheduler for
  > alpha-*-* targets and changes insn timings to reflect this.
  > 
  > This seems generate much better floating point code than the
  > old scheduler and seems to bootstrap.
  > 
  > I'd appreciate any feedback on these diffs from alpha hackers.  Thanks.
Richard Henderson installed changes into the last snapshot which
should be roughly equivalent, maybe even a little better.

Note we haven't made haifa the default scheduler for the alpha
though.  I'll leave that decision to Richard and the other
Alpha about when to make the switch.

jeff

<no subject>

[Joerg Beyer]

Hi,

I did some performance comparision of gcc 2.95.3 and gcc 3.1, each with
it's own libstdc++ and STLPort and a set of different compiler flags.

I compared the runtime of ~50 Testcases of C++ code, mainly small STL
using synthetic testcases with gcc 2.95.3 and the current 3.1. I used
gcc's libstdc++ and STLPort as well as a different compile time Flags
(from nothing to "-O3 -fexpensive-optimizations -fpeephole -march=i686
-fgcse -fomit-frame-pointer -funroll-loops").

to give you an idea: each testcase is a function that runs in less
than a second (usually 10th or 1000th times per second). The testcase
is called as long as a given time (e.g. 1 minute) is not over. The
number of calls to the testcase is counted (the loop counter), higher
loop counts are better results. The loop counts are compared for
each set of compile options.

Testcase focus on STL use, like reverse a std::list, appending
chars to a std::string, sorting a vector<int> and so on.

The results are here: http://cbench.sourceforge.net/log.html
you could get the source I used to gather the results here:
http://sourceforge.net/projects/cbench/

Feel free to contact me if you have questions.

Maybe this helps
Joerg

(no subject)

[Johannes Götz]

unsubscribe jgoetz@nepustil.net

(no subject)

[Johannes Götz]

help

(no subject)

[James Allchin]

subscribe

(no subject)

[Art Dickinson]

unsubscribe

(no subject)

[Jim Cole]

Success with egcs-1.0.3a

i586-pc-linux-gnulibc1

-- 
Jim Cole

greyleaf@yggdrasill.net

Re: (no subject)

[Jim Wilson]

	When I install egcs-1.0.2 on SGI R8000( irix6.1 ), I failed to compile
	enquire.c, error information as following:

	as ERROR:  /usr/lib64/cmplrs/asm died due to signal 10
	as ERROR:  core dumped

The gcc irix6 port emits N32 code by default, but Irix did not support N32
code until irix 6.2.  Unfortunately, there is no easy way to change the
default ABI, so gcc doesn't really support irix 6.0 and irix 6.1 anymore.

Ideally, we should have a separate configuration for irix6.[01], and make
that configuration default to N64 code.  The stuff that needs to be changed
is mostly in the config/mips/iris6.h file.  Change the *_DEFAULT* macros
at the top first, and then you may also need to modify some of the *_SPEC
macros.

Jim

(no subject)

[Chun Huang]

Hi,

When I install egcs-1.0.2 on SGI R8000( irix6.1 ), I failed to compile
enquire.c, error information as following:

 ./xgcc -B./  -DIN_GCC    -g -I./include     -DNO_MEM 
-DNO_LONG_DOUBLE_IO -O0 -I. -c ./enquire.c
./enquire.c: In function `cprop':
./enquire.c:1387: warning: comparison is always 0 due to limited 
range of data type
as ERROR:  /usr/lib64/cmplrs/asm died due to signal 10
as ERROR:  core dumped
*** Error code 1 (bu21)
*** Error code 1 (bu21)
*** Error code 1 (bu21)


Thanks in advance for your help.

Chun Huang

Re: (no subject)

[Jeffrey A Law]

  In message < 349677E4.2BC97DB1@tid.es >you write:
  > Where are the binutils for egcs-1.00 ?
  > I'm interested in all the stuff needed to create the BFD related
  > utilities, specially in the DLLTOOL, where I think I could have
  > some interesting ideas.
binutils is not part of egcs; you have to get them separately.

jeff

(no subject)

[Pedro A. Aranda Gutiirrez]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 579 bytes --]

Where are the binutils for egcs-1.00 ?
I'm interested in all the stuff needed to create the BFD related
utilities, specially in the DLLTOOL, where I think I could have
some interesting ideas.

--
####   Pedro Andres Aranda Gutierrez
####   ATM Networks Division
####   Telefonica I+D          C./ Emilio Vargas, 6
====                           E-28043 Madrid, Spain
====   mailto:paag@tid.es      Tlf +34-1-337 47 02
====                           FAX +34-1-337 45 02

"Theorie ist, wenn man weiß wie es geht"
"Praxis ist, wenn es geht, ohne daß man weiß wie"
Goethe

(no subject)

[Christopher J. Reimer]

subscribe reimer@doe.carleton.ca

(no subject)

[Jeffrey A Law]

subscribe egcs crux@Pool.Informatik.RWTH-Aachen.DE