* Using a umulhisi3
@ 2009-06-03 9:39 Michael Hope
2009-06-03 9:55 ` Julian Brown
0 siblings, 1 reply; 2+ messages in thread
From: Michael Hope @ 2009-06-03 9:39 UTC (permalink / raw)
To: gcc
[-- Attachment #1: Type: text/plain, Size: 3970 bytes --]
Hi there. The architecture I'm working is a 32 bit, word based
machine with a 16x16 -> 32 unsigned multiply. For some reason the
combine stage is converting the umulhisi3 into a mulsi3 and I'm not
sure how to track this down.
The test code is part of an alpha blend:
void blend(uint8_t* sb, uint8_t* db)
{
uint16_t ia = 256 - *sb;
uint16_t d = *db;
*db = ((d * ia) >> 8) + *sb;
}
I've define the different multiplies in the .md file:
(define_insn "umulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (zero_extend:SI
(match_operand:HI 1 "register_operand" "%r"))
(zero_extend:SI
(match_operand:HI 2 "register_operand" "r"))))]
""
...
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" "%r")
(match_operand:SI 2 "register_operand" "r")))]
""
...
Running at -O level optimisations gives the following in
umul.157r.outof_cfglayout, just before the combine stage:
---
(insn 3 6 4 2 umul.c:16 (set (reg/v/f:SI 28 [ sb ])
(reg:SI 0 R10 [ sb ])) 8 {movsi} (expr_list:REG_DEAD (reg:SI 0
R10 [ sb ])
(nil)))
(insn 4 3 5 2 umul.c:16 (set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ])) 8 {movsi} (expr_list:REG_DEAD (reg:SI 1
R11 [ db ])
(nil)))
(note 5 4 8 2 NOTE_INSN_FUNCTION_BEG)
(insn 8 5 9 2 umul.c:17 (set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg/v/f:SI 28 [ sb ]) [0 S1 A8]))) 27
{zero_extendqisi2} (expr_list:REG_DEAD (reg/v/f:SI 28 [ sb ])
(nil)))
(insn 9 8 10 2 umul.c:20 (set (reg:HI 30)
(const_int 256 [0x100])) 1 {movhi_insn} (nil))
(insn 10 9 11 2 umul.c:20 (set (reg:SI 31)
(minus:SI (subreg:SI (reg:HI 30) 0)
(reg:SI 26 [ D.1217 ]))) 12 {subsi3} (expr_list:REG_DEAD (reg:HI 30)
(nil)))
(insn 11 10 12 2 umul.c:20 (set (reg:SI 33)
(zero_extend:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]))) 27
{zero_extendqisi2} (nil))
(insn 12 11 13 2 umul.c:20 (set (reg:HI 32)
(subreg:HI (reg:SI 33) 0)) 1 {movhi_insn} (expr_list:REG_DEAD
(reg:SI 33)
(nil)))
(insn 13 12 14 2 umul.c:20 (set (reg:SI 34)
(mult:SI (zero_extend:SI (reg:HI 32))
(zero_extend:SI (subreg:HI (reg:SI 31) 0)))) 14
{umulhisi3} (expr_list:REG_DEAD (reg:HI 32)
(expr_list:REG_DEAD (reg:SI 31)
(nil))))
(insn 14 13 15 2 umul.c:20 (set (reg:SI 35)
(ashiftrt:SI (reg:SI 34)
(const_int 8 [0x8]))) 21 {ashrsi3_const}
(expr_list:REG_DEAD (reg:SI 34)
(nil)))
(insn 15 14 16 2 umul.c:20 (set (reg:QI 36)
(subreg:QI (reg:SI 35) 0)) 0 {movqi_insn} (expr_list:REG_DEAD
(reg:SI 35)
(nil)))
(insn 16 15 17 2 umul.c:20 (set (reg:SI 37)
(plus:SI (reg:SI 26 [ D.1217 ])
(subreg:SI (reg:QI 36) 0))) 11 {addsi3}
(expr_list:REG_DEAD (reg:QI 36)
(expr_list:REG_DEAD (reg:SI 26 [ D.1217 ])
(nil))))
(insn 17 16 0 2 umul.c:20 (set (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8])
(subreg:QI (reg:SI 37) 0)) 0 {movqi_insn} (expr_list:REG_DEAD
(reg:SI 37)
(expr_list:REG_DEAD (reg/v/f:SI 29 [ db ])
(nil))))
---
The umulhisi3 has been correctly found and used at this stage. In the
following combine stage however, it gets converted into a mulsi3. The
.combine dump is attached.
The xtensa port is the closest match I can find as it is 32 bit, word
based, and has the umulhisi3. It correctly keeps the 16 bit multiply.
Some other test cases like:
uint32_t mul(uint16_t a, uint16_t b)
{
return a*b;
}
come through fine. It might be something to do with the memory access.
How does the combine stage work? It looks like it could get multiple
potential matches for a set of RTLs. Does it use some type of costing
function to pick between them? Can I tell combine that a umulhisi3 is
cheaper than a mulsi3?
Thanks for the earlier help on the post reload split to use the
accumulator - it's working well.
-- Michael
[-- Attachment #2: umul.i.159r.combine --]
[-- Type: application/octet-stream, Size: 17932 bytes --]
;; Function blend (blend)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
insn_cost 3: 4
insn_cost 4: 4
insn_cost 8: 8
insn_cost 9: 12
insn_cost 10: 12
insn_cost 11: 8
insn_cost 12: 4
insn_cost 13: 40
insn_cost 14: 20
insn_cost 15: 4
insn_cost 16: 4
insn_cost 17: 4
Successfully matched this instruction:
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
deferring deletion of insn with uid = 3.
modifying insn i3 8 r26:SI=zero_extend([R10:SI])
REG_DEAD: R10:SI
deferring rescan insn with uid = 8.
Failed to match this instruction:
(parallel [
(set (reg:SI 31)
(minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 31)
(minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Failed to match this instruction:
(set (reg:SI 31)
(minus:SI (const_int 256 [0x100])
(reg:SI 26 [ D.1217 ])))
Failed to match this instruction:
(parallel [
(set (reg:SI 31)
(minus:SI (const_int 256 [0x100])
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 31)
(minus:SI (const_int 256 [0x100])
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Successfully matched this instruction:
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 31)
(minus:SI (const_int 256 [0x100])
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)))
Failed to match this instruction:
(parallel [
(set (reg:SI 33)
(zero_extend:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 33)
(zero_extend:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(set (reg:HI 32)
(zero_extend:HI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8])))
Failed to match this instruction:
(parallel [
(set (reg:HI 32)
(zero_extend:HI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(parallel [
(set (reg:HI 32)
(zero_extend:HI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Successfully matched this instruction:
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
Failed to match this instruction:
(set (reg:HI 32)
(zero_extend:HI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:QI (reg:HI 32) 0))
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(reg:SI 26 [ D.1217 ])) 0))))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(reg:SI 33)))
Failed to match this instruction:
(parallel [
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:QI (reg:HI 32) 0))
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)) 0))))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:QI (reg:HI 32) 0))
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)) 0))))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Successfully matched this instruction:
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:QI (reg:HI 32) 0))
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)) 0))))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:QI (reg:HI 32) 0))
(zero_extend:SI (subreg:HI (minus:SI (const_int 256 [0x100])
(reg:SI 26 [ D.1217 ])) 0))))
Failed to match this instruction:
(set (reg:SI 31)
(minus:SI (const_int 256 [0x100])
(reg:SI 26 [ D.1217 ])))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0)))
Successfully matched this instruction:
(set (reg:SI 32)
(zero_extend:SI (subreg:HI (reg:SI 31) 0)))
Successfully matched this instruction:
(set (reg:SI 34)
(mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0)))
deferring deletion of insn with uid = 11.
modifying insn i2 12 r32:SI=zero_extend(r31:SI#0)
REG_DEAD: r31:SI
deferring rescan insn with uid = 12.
modifying insn i3 13 r34:SI=r32:SI*[r29:SI]#0
REG_DEAD: r32:SI
deferring rescan insn with uid = 13.
Failed to match this instruction:
(set (reg:SI 32)
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(reg:SI 26 [ D.1217 ])) 0)))
Failed to match this instruction:
(parallel [
(set (reg:SI 32)
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)) 0)))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 32)
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)) 0)))
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
])
Successfully matched this instruction:
(set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8])))
Failed to match this instruction:
(set (reg:SI 32)
(zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(subreg:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]) 0)) 0)))
Failed to match this instruction:
(set (reg:SI 32)
(zero_extend:SI (subreg:HI (minus:SI (const_int 256 [0x100])
(reg:SI 26 [ D.1217 ])) 0)))
Failed to match this instruction:
(set (reg:SI 31)
(minus:SI (const_int 256 [0x100])
(reg:SI 26 [ D.1217 ])))
Failed to match this instruction:
(parallel [
(set (reg:SI 34)
(mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0)))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 34)
(mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0)))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0)))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (minus:SI (subreg:SI (reg:HI 30) 0)
(reg:SI 26 [ D.1217 ])) 0))
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0)))
Successfully matched this instruction:
(set (reg:SI 32)
(minus:SI (subreg:SI (reg:HI 30) 0)
(reg:SI 26 [ D.1217 ])))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (reg:SI 32) 0))
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0)))
Failed to match this instruction:
(parallel [
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0)))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0)))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Successfully matched this instruction:
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
Failed to match this instruction:
(set (reg:SI 34)
(mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0)))
Failed to match this instruction:
(set (reg:SI 35)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Failed to match this instruction:
(parallel [
(set (reg:SI 35)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(parallel [
(set (reg:SI 35)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Successfully matched this instruction:
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
Failed to match this instruction:
(set (reg:SI 35)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Failed to match this instruction:
(set (reg:SI 35)
(lshiftrt:SI (mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Successfully matched this instruction:
(set (reg:SI 34)
(zero_extend:SI (subreg:HI (reg:SI 31) 0)))
Failed to match this instruction:
(set (reg:SI 35)
(lshiftrt:SI (mult:SI (reg:SI 34)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Successfully matched this instruction:
(set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (reg:SI 34)
(const_int 8 [0x8])))
deferring deletion of insn with uid = 14.
modifying insn i3 15 r36:QI#0=r34:SI 0>>0x8
REG_DEAD: r34:SI
deferring rescan insn with uid = 15.
Failed to match this instruction:
(set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Failed to match this instruction:
(parallel [
(set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Failed to match this instruction:
(parallel [
(set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
])
Successfully matched this instruction:
(set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ]))
Failed to match this instruction:
(set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg:SI 1 R11 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Failed to match this instruction:
(set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (mult:SI (zero_extend:SI (subreg:HI (reg:SI 31) 0))
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Successfully matched this instruction:
(set (reg:SI 34)
(zero_extend:SI (subreg:HI (reg:SI 31) 0)))
Failed to match this instruction:
(set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (mult:SI (reg:SI 34)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8])))
Failed to match this instruction:
(set (reg:SI 37)
(plus:SI (lshiftrt:SI (reg:SI 34)
(const_int 8 [0x8]))
(reg:SI 26 [ D.1217 ])))
Failed to match this instruction:
(set (reg:SI 37)
(plus:SI (lshiftrt:SI (mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))
(const_int 8 [0x8]))
(reg:SI 26 [ D.1217 ])))
Successfully matched this instruction:
(set (reg:SI 36)
(mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0)))
Failed to match this instruction:
(set (reg:SI 37)
(plus:SI (lshiftrt:SI (reg:SI 36)
(const_int 8 [0x8]))
(reg:SI 26 [ D.1217 ])))
Failed to match this instruction:
(set (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8])
(subreg:QI (plus:SI (reg:SI 26 [ D.1217 ])
(subreg:SI (reg:QI 36) 0)) 0))
Failed to match this instruction:
(set (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8])
(subreg:QI (plus:SI (lshiftrt:SI (reg:SI 34)
(const_int 8 [0x8]))
(reg:SI 26 [ D.1217 ])) 0))
Successfully matched this instruction:
(set (reg:SI 37)
(lshiftrt:SI (reg:SI 34)
(const_int 8 [0x8])))
Failed to match this instruction:
(set (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8])
(subreg:QI (plus:SI (reg:SI 37)
(reg:SI 26 [ D.1217 ])) 0))
blend
Dataflow summary:
;; invalidated by call 0 [R10] 1 [R11] 2 [R12] 3 [R13] 15 [ACC] 16 [C] 17 [S] 18 [X] 19 [Y]
;; hardware regs used 13 [R1D] 14 [R1E]
;; regular block artificial uses 13 [R1D] 14 [R1E]
;; eh block artificial uses 13 [R1D] 14 [R1E]
;; entry block defs 0 [R10] 1 [R11] 13 [R1D] 14 [R1E]
;; exit block uses 13 [R1D] 14 [R1E]
;; regs ever live 0[R10] 1[R11]
;; ref usage r0={1d,1u} r1={1d,1u} r13={1d,2u} r14={1d,2u} r26={1d,2u} r28={1d,1u} r29={1d,2u} r30={1d,1u} r31={1d,1u} r32={1d,1u} r33={1d,1u} r34={1d,1u} r35={1d,1u} r36={1d,1u} r37={1d,1u}
;; total ref usage 34{15d,19u,0e} in 9{9 regular + 0 call} insns.
(note 1 0 6 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(13){ }u-1(14){ }}
;; lr in 0 [R10] 1 [R11] 13 [R1D] 14 [R1E]
;; lr use 0 [R10] 1 [R11] 13 [R1D] 14 [R1E]
;; lr def 26 28 29 30 31 32 33 34 35 36 37
;; Pred edge ENTRY [100.0%] (fallthru)
(note 6 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 3 6 4 2 NOTE_INSN_DELETED)
(insn 4 3 5 2 umul.c:16 (set (reg/v/f:SI 29 [ db ])
(reg:SI 1 R11 [ db ])) 8 {movsi} (expr_list:REG_DEAD (reg:SI 1 R11 [ db ])
(nil)))
(note 5 4 8 2 NOTE_INSN_FUNCTION_BEG)
(insn 8 5 9 2 umul.c:17 (set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (mem:QI (reg:SI 0 R10 [ sb ]) [0 S1 A8]))) 27 {zero_extendqisi2} (expr_list:REG_DEAD (reg:SI 0 R10 [ sb ])
(nil)))
(insn 9 8 10 2 umul.c:20 (set (reg:HI 30)
(const_int 256 [0x100])) 1 {movhi_insn} (nil))
(insn 10 9 11 2 umul.c:20 (set (reg:SI 31)
(minus:SI (subreg:SI (reg:HI 30) 0)
(reg:SI 26 [ D.1217 ]))) 12 {subsi3} (expr_list:REG_DEAD (reg:HI 30)
(nil)))
(note 11 10 12 2 NOTE_INSN_DELETED)
(insn 12 11 13 2 umul.c:20 (set (reg:SI 32)
(zero_extend:SI (subreg:HI (reg:SI 31) 0))) 28 {zero_extendhisi2} (expr_list:REG_DEAD (reg:SI 31)
(nil)))
(insn 13 12 14 2 umul.c:20 (set (reg:SI 34)
(mult:SI (reg:SI 32)
(subreg:SI (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8]) 0))) 13 {mulsi3} (expr_list:REG_DEAD (reg:SI 32)
(nil)))
(note 14 13 15 2 NOTE_INSN_DELETED)
(insn 15 14 16 2 umul.c:20 (set (subreg:SI (reg:QI 36) 0)
(lshiftrt:SI (reg:SI 34)
(const_int 8 [0x8]))) 23 {lshrsi3_const2} (expr_list:REG_DEAD (reg:SI 34)
(nil)))
(insn 16 15 17 2 umul.c:20 (set (reg:SI 37)
(plus:SI (reg:SI 26 [ D.1217 ])
(subreg:SI (reg:QI 36) 0))) 11 {addsi3} (expr_list:REG_DEAD (reg:QI 36)
(expr_list:REG_DEAD (reg:SI 26 [ D.1217 ])
(nil))))
(insn 17 16 0 2 umul.c:20 (set (mem:QI (reg/v/f:SI 29 [ db ]) [0 S1 A8])
(subreg:QI (reg:SI 37) 0)) 0 {movqi_insn} (expr_list:REG_DEAD (reg:SI 37)
(expr_list:REG_DEAD (reg/v/f:SI 29 [ db ])
(nil))))
;; End of basic block 2 -> ( 1)
;; lr out 13 [R1D] 14 [R1E]
;; Succ edge EXIT [100.0%] (fallthru)
starting the processing of deferred insns
deleting insn with uid = 3.
deleting insn with uid = 11.
deleting insn with uid = 14.
rescanning insn with uid = 8.
deleting insn with uid = 8.
rescanning insn with uid = 12.
deleting insn with uid = 12.
rescanning insn with uid = 13.
deleting insn with uid = 13.
rescanning insn with uid = 15.
deleting insn with uid = 15.
ending the processing of deferred insns
;; Combiner totals: 30 attempts, 30 substitutions (10 requiring new space),
;; 3 successes.
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: Using a umulhisi3
2009-06-03 9:39 Using a umulhisi3 Michael Hope
@ 2009-06-03 9:55 ` Julian Brown
0 siblings, 0 replies; 2+ messages in thread
From: Julian Brown @ 2009-06-03 9:55 UTC (permalink / raw)
To: Michael Hope; +Cc: gcc
On Wed, 3 Jun 2009 21:39:34 +1200
Michael Hope <michaelh@juju.net.nz> wrote:
> How does the combine stage work? It looks like it could get multiple
> potential matches for a set of RTLs. Does it use some type of costing
> function to pick between them? Can I tell combine that a umulhisi3 is
> cheaper than a mulsi3?
You could try defining TARGET_RTX_COSTS, if you haven't already.
Julian
^ permalink raw reply [flat|nested] 2+ messages in thread
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2009-06-03 9:39 Using a umulhisi3 Michael Hope
2009-06-03 9:55 ` Julian Brown
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