From: Andrew Stubbs <ams@codesourcery.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: gcc mailing list <gcc@gcc.gnu.org>
Subject: Re: Register allocation cost question
Date: Wed, 11 Oct 2023 15:49:08 +0100 [thread overview]
Message-ID: <47455696-961b-4e27-9ba2-4c85bbfa2037@codesourcery.com> (raw)
In-Reply-To: <20231010190930.GV19790@gate.crashing.org>
On 10/10/2023 20:09, Segher Boessenkool wrote:
> Hi Andrew,
>
> On Tue, Oct 10, 2023 at 04:11:18PM +0100, Andrew Stubbs wrote:
>> I'm also seeing wrong-code bugs when I allow more than 32 new registers,
>> but that might be an unrelated problem. Or the allocation is broken? I'm
>> still analyzing this.
>
> It could be connected. both things should not happen.
This is now confirmed to be unrelated: the instruction moving values
from the new registers to the old must be followed by a no-op in certain
instruction combinations due to GCN having only partial hardware
dependency detection.
The register allocation is therefore valid (at least in the testcases
I've been looking at).
The question of why it prefers registers with round numbers remains open
(and important for optimization reasons).
Andrew
next prev parent reply other threads:[~2023-10-11 14:49 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-10 15:11 Andrew Stubbs
2023-10-10 19:09 ` Segher Boessenkool
2023-10-11 8:57 ` Andrew Stubbs
2023-10-11 14:49 ` Andrew Stubbs [this message]
2023-10-11 6:54 ` Chung-Lin Tang
2023-10-11 8:58 ` Andrew Stubbs
2023-10-11 10:56 ` Richard Earnshaw (lists)
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