DI mode and endianess

DI mode and endianess

[Mohamed Shafi]

HI,

I am trying to port a 32bit target in GCC 4.4.0. My target supports
big and little endian. This is selected using a target switch. So i
have defined the macro

#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)

Currently i have written pattens only for SImode moves. So GCC will
synthesize DImode patterns for me. The problem is that GCC is
generating the same code for both big and little endian i.e  for the
following code

extern long long h;
extern long long j;
extern long long k;
int temp()
{
  k = j+h;
  return 0;
}

the compiler is generating the following code.

        section .text local
        ALIGN   16
        GLOBAL  _temp
_temp:
        mov  _h,d4
        mov  _h+4,d5
        mov  _j,d2
        mov  _j+4,d3
        add    d4,d2
        adc    d5,d3
        mov  d2,_k
        mov  d3,_k+4
        ret
        SIZE    _temp,*-_temp


irrespective of which endian it is.
What could i be missing here? Should i add anything specific for this
in the back-end?

Regards,
Shafi

Re: DI mode and endianess

[Richard Henderson]

On 08/19/2009 06:50 AM, Mohamed Shafi wrote:
>          mov  _h,d4
>          mov  _h+4,d5
>          mov  _j,d2
>          mov  _j+4,d3
>          add    d4,d2
>          adc    d5,d3
>
> irrespective of which endian it is.
> What could i be missing here? Should i add anything specific for this
> in the back-end?

Given that the compiler is generating adc, I have to
assume that you have an adddi3 pattern.  At which point
I have to assume that you're doing something wrong in
there that's producing the little-endian sequence even
for big-endian.


r~