From: Sebastian Huber <sebastian.huber@embedded-brains.de>
To: Richard Biener <richard.guenther@gmail.com>
Cc: GCC Development <gcc@gcc.gnu.org>
Subject: Re: -fprofile-update=atomic vs. 32-bit architectures
Date: Tue, 8 Nov 2022 07:22:11 +0100 [thread overview]
Message-ID: <582f9b96-47e9-6005-8d62-fd209f979848@embedded-brains.de> (raw)
In-Reply-To: <CAFiYyc0mP0_vJdcJCFKqToYEErBxyEZN++_KUWwxiF7w0AxA0w@mail.gmail.com>
On 05.11.22 12:18, Richard Biener wrote:
> On Fri, Nov 4, 2022 at 9:28 AM Sebastian Huber
> <sebastian.huber@embedded-brains.de> wrote:
>> Hello,
>>
>> even recent 32-bit architectures such as RISC-V do not support 64-bit
>> atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
>> RV32GC ISA yields:
>>
>> warning: target does not support atomic profile update, single mode is
>> selected
>>
>> For multi-threaded applications it is quite important to use atomic
>> counter increments to get valid coverage data. I think this fall back is
>> not really good. Maybe we should consider using this approach from Jakub
>> Jelinek for 32-bit architectures lacking 64-bit atomic operations:
>>
>> if (__atomic_add_fetch_4 ((unsigned int *) &val, 1, __ATOMIC_RELAXED)
>> == 0)
>> __atomic_fetch_add_4 (((unsigned int *) &val) + 1, 1,
>> __ATOMIC_RELAXED);
>>
>> https://patchwork.ozlabs.org/project/gcc/patch/19c4a81d-6ecd-8c6e-b641-e257c1959baf@suse.cz/#1447334
>>
>> Last year I added the TARGET_GCOV_TYPE_SIZE target hook to optionally
>> reduce the gcov type size to 32 bits. I am not really sure if this was a
>> good idea. Longer running executables may observe counter overflows
>> leading to invalid coverage data. If someone wants atomic updates, then
>> the updates should be atomic even if this means to use a library
>> implementation (libatomic).
>>
>> What about the following approach if -fprofile-update=atomic is given:
>>
>> 1. Use 64-bit atomics if available.
>>
>> 2. Use
>>
>> if (__atomic_add_fetch_4 ((unsigned int *) &val, 1, __ATOMIC_RELAXED)
>> == 0)
>> __atomic_fetch_add_4 (((unsigned int *) &val) + 1, 1,
>> __ATOMIC_RELAXED);
>>
>> if 32-bit atomics are available.
>>
>> 3. Else use a library call (libatomic).
> sounds good, though a library call would really be prohibitly expensive?
I someone wants to profile a multi-threaded application and selects
-fprofile-update=atomic, then probably a correct result is preferred.
You still have the option to select -fprofile-update=prefer-atomic.
For 2. I have to modify:
void
gimple_gen_edge_profiler (int edgeno, edge e)
{
tree one;
one = build_int_cst (gcov_type_node, 1);
if (flag_profile_update == PROFILE_UPDATE_ATOMIC)
{
/* __atomic_fetch_add (&counter, 1, MEMMODEL_RELAXED); */
tree addr = tree_coverage_counter_addr (GCOV_COUNTER_ARCS, edgeno);
tree f = builtin_decl_explicit (TYPE_PRECISION (gcov_type_node) > 32
? BUILT_IN_ATOMIC_FETCH_ADD_8:
BUILT_IN_ATOMIC_FETCH_ADD_4);
gcall *stmt = gimple_build_call (f, 3, addr, one,
build_int_cst (integer_type_node,
MEMMODEL_RELAXED));
gsi_insert_on_edge (e, stmt);
}
Is
if (WORDS_BIG_ENDIAN)
the right way to check for big/little endian?
How do I get ((unsigned int *) &val) + 1 from tree addr?
It would be great to have a code example for the construction of the "if
(f()) f();".
--
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next prev parent reply other threads:[~2022-11-08 6:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 8:27 Sebastian Huber
2022-11-04 9:53 ` Gabriel Paubert
2022-11-04 10:02 ` Sebastian Huber
2022-11-05 11:18 ` Richard Biener
2022-11-08 6:22 ` Sebastian Huber [this message]
2022-11-08 10:25 ` Richard Biener
2022-11-08 12:00 ` Sebastian Huber
2022-11-08 13:52 ` Richard Biener
2022-12-05 7:26 ` Sebastian Huber
2022-12-05 7:44 ` Richard Biener
2022-12-06 13:11 ` Sebastian Huber
2022-12-06 16:08 ` Richard Biener
2022-12-07 8:51 ` Sebastian Huber
2022-12-07 9:09 ` Richard Biener
2022-12-07 9:24 ` Sebastian Huber
2022-12-07 11:49 ` Richard Biener
2022-12-07 9:55 ` Sebastian Huber
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